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A case for shared instruction cache on chip multiprocessors running OLTP

Authors:

Partha Kundu,

Murali Annavaram,

Trung Diep,

John ShenAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 32, Issue 3

Pages 11 - 18

https://doi.org/10.1145/1024295.1024297

Published: 27 September 2003 Publication History

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Abstract

Due to their large code footprint, OLTP workloads suffer from significant I-cache miss rates on contemporary microprocessors. This paper analyzes the I-stream behavior of an OLTP workload, called the Oracle Database Benchmark (ODB), on Chip-Multiprocessors (CMP). Our results show that, although, the overall code footprint of ODB is large, multiple ODB threads running concurrently on multiple processors tend to access common code segments frequently, thus exhibiting significant constructive sharing. In fact, in a CMP system, an I-cache shared between multiple processors incurs similar miss rate as a dedicated I-cache per processor where the per processor I-cache has the same capacity as the shared I-cache. Based on these observations, this paper makes the case for a shared I-cache organization in a CMP, instead of the traditional approach of using a dedicated I-cache per processor.Furthermore, this paper shows that OLTP code stream exhibits good spatial locality. Adding a simple dedicated Line Buffer per processor can exploit this spatial locality effectively, to reduce latency and bandwidth requirements on the shared cache. The proposed shared I-cache organization results in an improvement of at least 5X in miss rate over a dedicated cache organization, for the same total capacity.

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Teng QZhong XLi YChen Y(2008)Performance Implications of Next-Generation Multi-processing Platforms on e-Business Server ApplicationsProceedings of the 2008 IEEE International Conference on e-Business Engineering10.1109/ICEBE.2008.13(37-44)Online publication date: 22-Oct-2008
https://dl.acm.org/doi/10.1109/ICEBE.2008.13
Shayesteh AReinman GJouppi NSherwood TSair SHong SWolf WFlautner KKim T(2006)Improving the performance and power efficiency of shared helpers in CMPsProceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems10.1145/1176760.1176802(345-356)Online publication date: 22-Oct-2006
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Saylor GKhessib BAilamaki ABoncz PManegold S(2006)Large scale Itanium® 2 processor OLTP workload characterization and optimizationProceedings of the 2nd international workshop on Data management on new hardware10.1145/1140402.1140406(3-es)Online publication date: 25-Jun-2006
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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 32, Issue 3

Special issue: MEDEA-2003 workshop

June 2004

81 pages

ISSN:0163-5964

DOI:10.1145/1024295

Issue’s Table of Contents

MEDEA '03: Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
September 2003
75 pages
ISBN:9781450378208
DOI:10.1145/1152923
Conference Chairs:
Sandro Bartolini
University of Siena, Italy
,
Pierfrancesco Foglia
University of Pisa, Italy
,
Roberto Giorgi
University of Siena, Italy
,
Cosimo Antonio Prete
University of Pisa, Italy

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 27 September 2003

Published in SIGARCH Volume 32, Issue 3

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Teng QZhong XLi YChen Y(2008)Performance Implications of Next-Generation Multi-processing Platforms on e-Business Server ApplicationsProceedings of the 2008 IEEE International Conference on e-Business Engineering10.1109/ICEBE.2008.13(37-44)Online publication date: 22-Oct-2008
https://dl.acm.org/doi/10.1109/ICEBE.2008.13
Shayesteh AReinman GJouppi NSherwood TSair SHong SWolf WFlautner KKim T(2006)Improving the performance and power efficiency of shared helpers in CMPsProceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems10.1145/1176760.1176802(345-356)Online publication date: 22-Oct-2006
https://dl.acm.org/doi/10.1145/1176760.1176802
Saylor GKhessib BAilamaki ABoncz PManegold S(2006)Large scale Itanium® 2 processor OLTP workload characterization and optimizationProceedings of the 2nd international workshop on Data management on new hardware10.1145/1140402.1140406(3-es)Online publication date: 25-Jun-2006
https://dl.acm.org/doi/10.1145/1140402.1140406
Shayesteh AReinman GJouppi NSair SSherwood T(2005)Dynamically configurable shared CMP helper engines for improved performanceACM SIGARCH Computer Architecture News10.1145/1105734.110574433:4(70-79)Online publication date: 1-Nov-2005
https://dl.acm.org/doi/10.1145/1105734.1105744
Beckmann BWood D(2004)Managing Wire Delay in Large Chip-Multiprocessor CachesProceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2004.21(319-330)Online publication date: 4-Dec-2004
https://dl.acm.org/doi/10.1109/MICRO.2004.21
Wang JRamrakhyani PElsasser WJohn L(2019)Reducing Data Movement and Energy in Multilevel Cache Hierarchies without Losing Performance: Can you have it all?Proceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2019.00037(382-393)Online publication date: 23-Sep-2019
https://dl.acm.org/doi/10.1109/PACT.2019.00037
Milic URico ACarpenter PRamirez A(2017)Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS.2017.7975265(3-12)Online publication date: Apr-2017
https://doi.org/10.1109/ISPASS.2017.7975265

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