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Cache optimization for embedded processor cores: An analytical approach

Authors:

Tony GivargisAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 9, Issue 4

Pages 419 - 440

https://doi.org/10.1145/1027084.1027086

Published: 01 October 2004 Publication History

Abstract

Embedded microprocessor cores are increasingly being used in embedded and mobile devices. The software running on these embedded microprocessor cores is often a priori known; thus, there is an opportunity for customizing the cache subsystem for improved performance. In this work, we propose an efficient algorithm to directly compute cache parameters satisfying desired performance criteria. Our approach avoids simulation and exhaustive exploration, and, instead, relies on an exact algorithmic approach. We demonstrate the feasibility of our algorithm by applying it to a large number of embedded system benchmarks.

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Cited By

Mehrabi AManocha ALee BSorin D(2020)Bayesian Optimization for Efficient Accelerator SynthesisACM Transactions on Architecture and Code Optimization10.1145/342737718:1(1-25)Online publication date: 30-Dec-2020
https://dl.acm.org/doi/10.1145/3427377
Badreldin IGordon-Ross AAdegbija TAlsafrjalaniz M(2018)Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00136(719-725)Online publication date: Jul-2018
https://doi.org/10.1109/ISVLSI.2018.00136
Liang YWang SMitra THa Y(2018)Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical ApplicationsAdvanced Computer Architecture10.1007/978-981-13-2423-9_8(95-108)Online publication date: 13-Sep-2018
https://doi.org/10.1007/978-981-13-2423-9_8
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Index Terms

Cache optimization for embedded processor cores: An analytical approach
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 9, Issue 4

October 2004

144 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1027084

Issue’s Table of Contents

Copyright © 2004 ACM.

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 October 2004

Published in TODAES Volume 9, Issue 4

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Cited By

Mehrabi AManocha ALee BSorin D(2020)Bayesian Optimization for Efficient Accelerator SynthesisACM Transactions on Architecture and Code Optimization10.1145/342737718:1(1-25)Online publication date: 30-Dec-2020
https://dl.acm.org/doi/10.1145/3427377
Badreldin IGordon-Ross AAdegbija TAlsafrjalaniz M(2018)Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00136(719-725)Online publication date: Jul-2018
https://doi.org/10.1109/ISVLSI.2018.00136
Liang YWang SMitra THa Y(2018)Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical ApplicationsAdvanced Computer Architecture10.1007/978-981-13-2423-9_8(95-108)Online publication date: 13-Sep-2018
https://doi.org/10.1007/978-981-13-2423-9_8
Gianelli SAdegbija T(2017)PACT: Priority-Aware Phase-Based Cache Tuning for Embedded Systems2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2017.77(403-408)Online publication date: Jul-2017
https://doi.org/10.1109/ISVLSI.2017.77
Wingbermuehle JCytron RChamberlain RConstantinides GChen D(2015)Superoptimized Memory Subsystems for Streaming ApplicationsProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689069(126-135)Online publication date: 22-Feb-2015
https://dl.acm.org/doi/10.1145/2684746.2689069
Schneider JPeddersen JParameswaran S(2015)Speeding up single pass simulation of PLRUt cachesThe 20th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2015.7059091(695-700)Online publication date: Jan-2015
https://doi.org/10.1109/ASPDAC.2015.7059091
Wingbermuehle JCytron RChamberlain R(2015)Superoptimizing Memory Subsystems for Multiple ObjectivesEuro-Par 2015: Parallel Processing Workshops10.1007/978-3-319-27308-2_29(352-363)Online publication date: 18-Dec-2015
https://doi.org/10.1007/978-3-319-27308-2_29
Wingbermuehle JCytron RChamberlain R(2014)Superoptimization of memory subsystemsACM SIGPLAN Notices10.1145/2666357.259781649:5(145-154)Online publication date: 12-Jun-2014
https://dl.acm.org/doi/10.1145/2666357.2597816
Wingbermuehle JCytron RChamberlain RZhang YKulkarni P(2014)Superoptimization of memory subsystemsProceedings of the 2014 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems10.1145/2597809.2597816(145-154)Online publication date: 12-Jun-2014
https://dl.acm.org/doi/10.1145/2597809.2597816
Schneider JPeddersen JParameswaran S(2014)MASH{fifo}Proceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593159(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593159
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