article

Reusing an on-chip network for the test of core-based systems

Authors:

Marcelo LubaszewskiAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 9, Issue 4

Pages 471 - 499

https://doi.org/10.1145/1027084.1027088

Published: 01 October 2004 Publication History

Abstract

Networks-on-chip are likely to become the main communication platform of systems-on-chip. To cope with the growing complexity of the test of such systems, the authors propose the reuse of the on-chip network as a test access mechanism to the cores embedded into systems that use this communication platform. An algorithm exploiting the network characteristics to minimize test time is presented. Then, the reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results for the ITC'02 SOC Test Benchmarks show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.

References

[1]

Aktouf, C. 2002. A complete strategy for testing an on-chip multiprocessor architecture. IEEE Design & Test of Computers 19, 1 (Jan--Feb), 18--28.

[2]

Benini, L. and Micheli, G. D. 2002. Networks on chips: A new SOC paradigm. IEEE Comput. 35, 1 (Jan.), 70--78.

[3]

Bhattacharya, D. 1998. Hierarchical test access architecture for embedded cores in an integrated circuit. In Proceedings of the 16th IEEE VLSI Test Symposium (Los Alamitos, Calif.). IEEE Computer Society, Los Alamitos, Calif., 8--14.

[4]

Cota, E., Carro, L., Orailoglu, A., and Lubaszewski, M. 2002. Test planning and design space exploration in core-based environment. In Proceedings of the Design, Automation and Test in Europe (Paris, France). IEEE Computer Society, Press, Los Alamitos, Calif., 483--490.

[5]

Cota, E., Zeferino, C., Kreutz, M., Carro, L., Lubaszewski, M., and Susin, A. 2003. The impact of NoC reuse on the testing of core-based systems. In Proceedings of the IEEE VLSI Test Symposium (Napa Valley, Calif.). IEEE Computer Society, Press, Los Alamitos, Calif., 128--133.

[6]

Dally, W. J. and Towles, B. 2001. Route packets, not wires: On-chip interconnection networks. In Design Automation Conference. ACM, New York, 684--689.

[7]

Duato, J., Yalamanchili, S., and Ni, L. 1997. Interconnection Networks: An Engineering Approach. IEEE Computer Society, Press, Los Alamitos, Calif.

[8]

Gerez, S. H. 1998. Algorithms for VLSI Design Automation. Baffins Lane, Chichester, England, Wiley.

[9]

Ghosh, I., Jha, N., and Dey, S. 1997. A low overhead design for testability and test generation technique for core-based systems. In International Test Conference (Washington, D.C.). IEEE Computer Society, Press, Los Alamitos, Calif., 50--59.

[10]

Goel, S. and Marinissen, E. 2002. Effective and efficient test architecture design for SOCs. In Proceedings of the International Test Conference. IEEE Computer Society, Press, Los Alamitos, Calif., 529--538.

[11]

Guerrier, P. and Greiner, A. 2000. A generic architecture for on-chip packet-switched interconnections. In Proceedings of the Design, Automation and Test in Europe (Paris, France). IEEE Computer Society, Press, Los Alamitos, Calif., 250--256.

[12]

Iyengar, V. 2001. Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip. In Proceedings of the IEEE VLSI Test Symposium, Los Angeles, Calif., IEEE Computer Society, Press, Los Alamitos, Calif., 368--374.

[13]

Iyengar, V., Chakrabarty, K., and Marinissen, E. 2002. Efficient wrapper/TAM co-optimization for large SOCs. In Proceedings of the Design, Automation and Test in Europe (Paris, France). IEEE Computer Society, Paris, FR, 491--498.

[14]

Iyengar, V., Chakrabarty, K., and Marinissen, E. J. 2001. Iterative test wrapper and test access mechanism co-optimization. In Proceedings of the International Test Conference (Baltimore, Md.). IEEE Computer Society, Los Alamitos, Calif., 1023--1032.

[15]

Larsson, E. and Fujiwara, H. 2002. Power constrained preemptive TAM scheduling. In Proceedings of the 7th IEEE European Test Workshop. IEEE Computer Society, Press, Los Alamitos, Calif., 119--126.

[16]

Larsson, E. and Peng, Z. 2001. An integrated system-on-chip test framework. In Proceedings of the Design, Automation and Test in Europe Conference (Munich, Germany). IEEE Computer Society, Press, Los Alamitos, Calif., 138--144.

[17]

Marinissen, E., Arendsen, R., Bos, G., Dingemanse, H., Lousberg, M., and Wouters, C. 1998. A structured and scalable mechanism for test access to embedded reusable cores. In Proceedings of the International Test Conference (Los Alamitos). IEEE Computer Society, Press, Los Alamitos, Calif., 284--293.

[18]

Marinissen, E. J., Iyengar, V., and Chakrabarty, K. 2002. A set of benchmarks for modular testing of SOCs. In Proceedings of the International Test Conference. IEEE Computer Society, Press, Los Alamitos, Calif., 521--528.

[19]

Marinissen, E. J., Iyengar, V., and Chakrabarty, K. 2003. ITC'02 Soc test benchmarks. Tech. rep. Available at: http://www.extra.research.philips.com/itc02socbenchm/. Acessed in: August 2003.

[20]

Marinissen, E. J., Kapur, R., and Zorian, Y. 2000. On using IEEE P1500 SECT for test plug-n-play. In Proceedings of the International Test Conference. IEEE Computer Society, Press, Los Alamitos, Calif., 770--777.

[21]

Nahvi, M. and Ivanov, A. 2001. A packet switching communication-based test access mechanism for system chips. In Proceedings of the IEEE European Test Workshop. IEEE Computer Society, Press, Los Alamitos, Calif., 81--86.

[22]

Nourani, M. and Papachristou, C. 1999. Structural fault testing of embedded cores using pipelining. J. Electron. Test.: Theory Appl. 15, 1-2 (Aug.--Oct.), 129--144.

[23]

Ravi, S., Lakshminarayana, G., and Jha, N. 2001. Testing of core-based systems-on-a-chip. IEEE Trans. Comput. Aid. Desi. Integ. Circ. Syst. 20, 3 (Mar.), 426--439.

[24]

Whetsel, L. 1997. An IEEE 1149.1 based test access architecture for ICs with embedded cores. In Proceedings of the International Test Conference (Washington, D.C.). IEEE Computer Society, Press, Los Alamitos, Calif., 69--78.

[25]

Zeferino, C., Kreutz, M., Carro, L., and Susin, A. 2002. A study on communication issues for systems-on-chip. In Proceedings of the Symposium on Integrated Circuits and Systems Design (Parto Alegre, Brazil). IEEE Computer Society, Press, Los Alamitos, Calif., 121--126.

[26]

Zeferino, C. and Susin, A. 2003. SoCIN: A parametric and scalable network-on-chip. In Proceedings of the Symposium on Integrated Circuits and Systems Design (São Paulo, Brazil). IEEE Computer Society, Press, Los Alamitos, Calif., 169--174.

[27]

Zorian, Y. 1997. Test requirements for embedded core-based systems and IEEE P1500. In Proceedings of the International Test Conference (Washington, D.C.). IEEE Computer Society, Press, Los Alamitos, Calif., 191--199.

Cited By

Aghaei BReshadi MMasdari MSajadi SHosseinzadeh MDarwesh A(2020)Network adapter architectures in network on chip: comprehensive literature reviewCluster Computing10.1007/s10586-019-02924-223:1(321-346)Online publication date: 1-Mar-2020
https://dl.acm.org/doi/10.1007/s10586-019-02924-2
Seidemann MGlombiewski NKörber MSeeger B(2019)ChronicleDBACM Transactions on Database Systems10.1145/334235744:4(1-45)Online publication date: 15-Oct-2019
https://dl.acm.org/doi/10.1145/3342357
Martens WTrautner T(2019)Dichotomies for Evaluating Simple Regular Path QueriesACM Transactions on Database Systems10.1145/333144644:4(1-46)Online publication date: 15-Oct-2019
https://dl.acm.org/doi/10.1145/3331446
Show More Cited By

Index Terms

Reusing an on-chip network for the test of core-based systems
1. Hardware
  1. Hardware test
  2. Robustness

Recommendations

Reducing test time with processor reuse in network-on-chip based systems
SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design

This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores embedded into a system on chip. The resulting test time of the system is ...
SOC test architecture design for efficient utilization of test bandwidth

This article deals with the design of on-chip architectures for testing large system chips (SOCs) for manufacturing defects in a modular fashion. These architectures consist of wrappers and test access mechanisms (TAMs). For an SOC with specified ...
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints
ASP-DAC '09: Proceedings of the 2009 Asia and South Pacific Design Automation Conference

We present a thermal-aware test-access mechanism (TAM) design and test scheduling method for system-on-chip (SOC) integrated circuits. The proposed method uses cycle-accurate power profiles for thermal simulation; it also relies on test-set partitioning,...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 9, Issue 4

October 2004

144 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1027084

Issue’s Table of Contents

Copyright © 2004 ACM.

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 October 2004

Published in TODAES Volume 9, Issue 4

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

76
Total Citations
View Citations
1,656
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)0

Reflects downloads up to 03 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Aghaei BReshadi MMasdari MSajadi SHosseinzadeh MDarwesh A(2020)Network adapter architectures in network on chip: comprehensive literature reviewCluster Computing10.1007/s10586-019-02924-223:1(321-346)Online publication date: 1-Mar-2020
https://dl.acm.org/doi/10.1007/s10586-019-02924-2
Seidemann MGlombiewski NKörber MSeeger B(2019)ChronicleDBACM Transactions on Database Systems10.1145/334235744:4(1-45)Online publication date: 15-Oct-2019
https://dl.acm.org/doi/10.1145/3342357
Martens WTrautner T(2019)Dichotomies for Evaluating Simple Regular Path QueriesACM Transactions on Database Systems10.1145/333144644:4(1-46)Online publication date: 15-Oct-2019
https://dl.acm.org/doi/10.1145/3331446
Brijder RGeerts FBussche JWeerwag T(2019)On the Expressive Power of Query Languages for MatricesACM Transactions on Database Systems10.1145/333144544:4(1-31)Online publication date: 15-Oct-2019
https://dl.acm.org/doi/10.1145/3331445
Karabacak FOgras UOzev S(2018)Remote Detection of Unauthorized Activity via Spectral AnalysisACM Transactions on Design Automation of Electronic Systems10.1145/327677023:6(1-21)Online publication date: 28-Nov-2018
https://dl.acm.org/doi/10.1145/3276770
Yang KBotero UShen HWoodard DForte DTehranipoor M(2018)UCRACM Transactions on Design Automation of Electronic Systems10.1145/326465823:6(1-24)Online publication date: 28-Nov-2018
https://dl.acm.org/doi/10.1145/3264658
Xiang DChakrabarty KFujiwara H(2018)Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip TestingACM Transactions on Design Automation of Electronic Systems10.1145/324321423:6(1-23)Online publication date: 6-Dec-2018
https://dl.acm.org/doi/10.1145/3243214
Chang DBhat GOgras UBakkaloglu BOzev S(2018)Detection Mechanisms for Unauthorized Wireless TransmissionsACM Transactions on Design Automation of Electronic Systems10.1145/324104623:6(1-21)Online publication date: 6-Nov-2018
https://dl.acm.org/doi/10.1145/3241046
Eslami FWilton S(2018)Rapid Triggering Capability Using an Adaptive Overlay during FPGA DebugACM Transactions on Design Automation of Electronic Systems10.1145/324104523:6(1-25)Online publication date: 6-Dec-2018
https://dl.acm.org/doi/10.1145/3241045
Hussain SKoushanfar F(2018)P3ACM Transactions on Design Automation of Electronic Systems10.1145/323662523:6(1-19)Online publication date: 28-Nov-2018
https://dl.acm.org/doi/10.1145/3236625
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Issue’s Table of Contents