Article

The effect of post-layout pin permutation on timing

Authors:

Nanchi ChouAuthors Info & Claims

FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

Pages 41 - 50

https://doi.org/10.1145/1046192.1046199

Published: 20 February 2005 Publication History

Abstract

In this paper we study the effect of post-layout pin permutation of designs for FPGA devices with non-uniform cell delays. We present a simple, but timing optimal, pin permutation scheme, and report the results of applying the scheme on a set of public logic synthesis benchmark designs that were synthesized and placed by state-of-the-art commercial FPGA design tools configured to maximum optimization level. Despite the preceding optimizations, we still observed an average timing improvement of 3.7%. This demonstrates the importance of fully utilizing non-uniform cell delays during design optimizations for modern FPGA devices and the still presenting potential of improvement.

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Cited By

Greene JIenne PZhang Z(2023)FPGA Mux Usage and Routability Estimates without Explicit RoutingProceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3543622.3573045(141-147)Online publication date: 12-Feb-2023
https://dl.acm.org/doi/10.1145/3543622.3573045
Hutton MBetz VAnderson J(2016)FPGA Synthesis and Physical DesignElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-18(373-413)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-18
Zhu KDeHon AHutton M(2007)Post-route LUT output polarity selection for timing optimizationProceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays10.1145/1216919.1216932(89-96)Online publication date: 18-Feb-2007
https://dl.acm.org/doi/10.1145/1216919.1216932

Index Terms

The effect of post-layout pin permutation on timing
1. Hardware

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cover image ACM Conferences

FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

February 2005

288 pages

ISBN:1595930299

DOI:10.1145/1046192

General Chair:
Herman Schmit
Tabula
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Program Chair:
Steve Wilton
University of British Columbia

Copyright © 2005 ACM.

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Publication History

Published: 20 February 2005

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FPGA05: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2005

February 20 - 22, 2005

California, Monterey, USA

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Cited By

Greene JIenne PZhang Z(2023)FPGA Mux Usage and Routability Estimates without Explicit RoutingProceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3543622.3573045(141-147)Online publication date: 12-Feb-2023
https://dl.acm.org/doi/10.1145/3543622.3573045
Hutton MBetz VAnderson J(2016)FPGA Synthesis and Physical DesignElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-18(373-413)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-18
Zhu KDeHon AHutton M(2007)Post-route LUT output polarity selection for timing optimizationProceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays10.1145/1216919.1216932(89-96)Online publication date: 18-Feb-2007
https://dl.acm.org/doi/10.1145/1216919.1216932

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