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The effect of post-layout pin permutation on timing

Published: 20 February 2005 Publication History

Abstract

In this paper we study the effect of post-layout pin permutation of designs for FPGA devices with non-uniform cell delays. We present a simple, but timing optimal, pin permutation scheme, and report the results of applying the scheme on a set of public logic synthesis benchmark designs that were synthesized and placed by state-of-the-art commercial FPGA design tools configured to maximum optimization level. Despite the preceding optimizations, we still observed an average timing improvement of 3.7%. This demonstrates the importance of fully utilizing non-uniform cell delays during design optimizations for modern FPGA devices and the still presenting potential of improvement.

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Cited By

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  • (2023)FPGA Mux Usage and Routability Estimates without Explicit RoutingProceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3543622.3573045(141-147)Online publication date: 12-Feb-2023
  • (2016)FPGA Synthesis and Physical DesignElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-18(373-413)Online publication date: 14-Apr-2016
  • (2007)Post-route LUT output polarity selection for timing optimizationProceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays10.1145/1216919.1216932(89-96)Online publication date: 18-Feb-2007

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cover image ACM Conferences
FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
February 2005
288 pages
ISBN:1595930299
DOI:10.1145/1046192
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 20 February 2005

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Author Tags

  1. FPGA
  2. logic synthesis
  3. placement
  4. timing optimization

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Cited By

View all
  • (2023)FPGA Mux Usage and Routability Estimates without Explicit RoutingProceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3543622.3573045(141-147)Online publication date: 12-Feb-2023
  • (2016)FPGA Synthesis and Physical DesignElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-18(373-413)Online publication date: 14-Apr-2016
  • (2007)Post-route LUT output polarity selection for timing optimizationProceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays10.1145/1216919.1216932(89-96)Online publication date: 18-Feb-2007

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