Article

Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs

Authors:

Nicola Campregher,

Peter Y. K. Cheung,

George A. Constantinides,

Milan VasilkoAuthors Info & Claims

FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

Pages 138 - 148

https://doi.org/10.1145/1046192.1046211

Published: 20 February 2005 Publication History

Abstract

This paper presents an analysis of the potential yield loss in FPGA due to random defects in metal layers. A proven yield model is adapted to target the FPGA interconnect layers in order to predict the manufacturing yield. Defect parameters from the 2003 SIA roadmap are used to investigate the trend in yield loss due to defects in interconnect layers in the future. It is shown that the low yield predicted for the 45nm technology node and beyond is a cause for concern. The potential impact on yield using two different approaches, namely redundant circuits and fault tolerant design, is also presented.

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Index Terms

Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs
1. Hardware
  1. Hardware test
  2. Robustness
    1. Hardware reliability

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cover image ACM Conferences

FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

February 2005

288 pages

ISBN:1595930299

DOI:10.1145/1046192

General Chair:
Herman Schmit
Tabula
,
Program Chair:
Steve Wilton
University of British Columbia

Copyright © 2005 ACM.

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Published: 20 February 2005

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FPGA05: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2005

February 20 - 22, 2005

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Chaudhuri ABanerjee SKim JLim SChakrabarty K(2023)Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.322885031:3(296-309)Online publication date: Mar-2023
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Chaudhuri ABanerjee SKim JPark HKu BKannan SChakrabarty KLim S(2021)Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICsACM Journal on Emerging Technologies in Computing Systems10.1145/346443018:1(1-37)Online publication date: 3-Nov-2021
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