Article

Efficient static timing analysis and applications using edge masks

Authors:

David Karchmer,

Jason GovigAuthors Info & Claims

FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

Pages 174 - 183

https://doi.org/10.1145/1046192.1046215

Published: 20 February 2005 Publication History

Abstract

Static timing analysis (STA) with multiple clock domains and complicated exception conditions is a complex practical problem that can dramatically increase compilation time, both for back-end analysis and during place and route. In FPGA placement, timing analysis with many constraints can dominate placement run-time.In this paper we introduce a simple binary edge-mask data structure on arcs in a timing netlist which allows for efficient timing analysis in the presence of many such constraints. The technique applies to either BFS or DFS-based timing analysis. Preliminary implementations on just the basic concept show a 59% decrease in STA run-time for multi-clock designs, indicating that significant benefit is to be gained from a complete implementation. On a set of heavily constrained designs this benefit improved to 80% run-time decrease.Further applications of the edge-mask concept are shown to efficiently deal with thru-x constraints, enumerating the k-longest paths in a timing graph, and partial/incremental timing analysis aimed at significant improvements in placement time.

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D. Blaauw et. al., "Slope Propagation in Static Timing Analysis", in Proc. ICCAD, 2000.

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Cited By

Boutros ABetz V(2024)Field-Programmable Gate Array ArchitectureHandbook of Computer Architecture10.1007/978-981-97-9314-3_49(417-463)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-981-97-9314-3_49
Yuan LYou HGuo G(2023)System Static Timing Analysis Method Based on Hierarchization2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218386(179-183)Online publication date: 8-May-2023
https://doi.org/10.1109/ISEDA59274.2023.10218386
Boutros ABetz V(2023)Field-Programmable Gate Array ArchitectureHandbook of Computer Architecture10.1007/978-981-15-6401-7_49-1(1-47)Online publication date: 7-Jan-2023
https://doi.org/10.1007/978-981-15-6401-7_49-1
Show More Cited By

Index Terms

Efficient static timing analysis and applications using edge masks
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory

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Published In

cover image ACM Conferences

FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

February 2005

288 pages

ISBN:1595930299

DOI:10.1145/1046192

General Chair:
Herman Schmit
Tabula
,
Program Chair:
Steve Wilton
University of British Columbia

Copyright © 2005 ACM.

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Publication History

Published: 20 February 2005

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FPGA05

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FPGA05: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2005

February 20 - 22, 2005

California, Monterey, USA

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Cited By

Boutros ABetz V(2024)Field-Programmable Gate Array ArchitectureHandbook of Computer Architecture10.1007/978-981-97-9314-3_49(417-463)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-981-97-9314-3_49
Yuan LYou HGuo G(2023)System Static Timing Analysis Method Based on Hierarchization2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218386(179-183)Online publication date: 8-May-2023
https://doi.org/10.1109/ISEDA59274.2023.10218386
Boutros ABetz V(2023)Field-Programmable Gate Array ArchitectureHandbook of Computer Architecture10.1007/978-981-15-6401-7_49-1(1-47)Online publication date: 7-Jan-2023
https://doi.org/10.1007/978-981-15-6401-7_49-1
Mohajer SWang ZBazargan KLi Y(2020)Parallel Unary Computing Based on Function DerivativesACM Transactions on Reconfigurable Technology and Systems10.1145/341846414:1(1-25)Online publication date: 28-Oct-2020
https://dl.acm.org/doi/10.1145/3418464
Beasley AClarke CWatson R(2020)An OpenGL Compliant Hardware Implementation of a Graphic Processing Unit Using Field Programmable Gate Array–System on Chip TechnologyACM Transactions on Reconfigurable Technology and Systems10.1145/341035714:1(1-24)Online publication date: 2-Sep-2020
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https://dl.acm.org/doi/10.1145/3409113
Murray KPetelin OZhong SWang JEldafrawy MLegault JSha EGraham AWu JWalker MZeng HPatros PLuu JKent KBetz V(2020)VTR 8ACM Transactions on Reconfigurable Technology and Systems10.1145/338861713:2(1-55)Online publication date: 1-Jun-2020
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Kourfali AStroobandt D(2020)In-Circuit Debugging with Dynamic Reconfiguration of FPGA InterconnectsACM Transactions on Reconfigurable Technology and Systems10.1145/337545913:1(1-29)Online publication date: 30-Jan-2020
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Attia SBetz V(2020)Feel Free to InterruptACM Transactions on Reconfigurable Technology and Systems10.1145/337249113:1(1-27)Online publication date: 28-Jan-2020
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Tridgell SKumm MHardieck MBoland DMoss DZipf PLeong P(2019)Unrolling Ternary Neural NetworksACM Transactions on Reconfigurable Technology and Systems10.1145/335998312:4(1-23)Online publication date: 18-Oct-2019
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