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Synthesis of application-specific highly efficient multi-mode cores for embedded systems

Published: 01 February 2005 Publication History

Abstract

In this paper, we present a novel design methodology for synthesizing multiple configurations (or modes) into a single programmable core that can be used in embedded systems. Recent portable applications require reconfigurability of a system along with efficiency in terms of power, performance, and area. The field programmable gate arrays (FPGAs) provide a reconfigurable platform; however, they are slower in speed with significantly higher power and area than achievable by a customized application-specific integrated circuits (ASIC). Implementation of a system in either FPGA or ASIC represents a trade-off between programmability and design efficiency. In this work, we have developed techniques to realize efficient reconfigurable cores for a set of user-specified applications. The resultant system, named as multimode system, can easily switch configurations throughout the set of configurations it is designed for. A data flow graph transformation method coupled with efficient scheduling and allocation is used to automatically synthesize a Multi-Mode system from its behavior-level specifications. Experimental results on several applications demonstrate that our implementations can achieve about 60X power reduction on average and run 3.5X faster over corresponding FPGA implementations.

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  • (2016)“Multi-Circuit”: Automatic Generation of an Application Specific Configurable Core for Known Set of Application CircuitsJournal of Circuits, Systems and Computers10.1142/S021812661650102425:09(1650102)Online publication date: Sep-2016
  • (2014)A top-down optimization methodology for mutually exclusive applicationsInternational Journal of Reconfigurable Computing10.1155/2014/8276132014(3-3)Online publication date: 1-Jan-2014
  • (2012)On the asymptotic costs of multiplexer-based reconfigurabilityProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228503(790-795)Online publication date: 3-Jun-2012
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Published In

cover image ACM Transactions on Embedded Computing Systems
ACM Transactions on Embedded Computing Systems  Volume 4, Issue 1
February 2005
254 pages
ISSN:1539-9087
EISSN:1558-3465
DOI:10.1145/1053271
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Association for Computing Machinery

New York, NY, United States

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Publication History

Published: 01 February 2005
Published in TECS Volume 4, Issue 1

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Author Tags

  1. Digital signal processing (DSP)
  2. application specific integrated circuits (ASIC)
  3. embedded systems
  4. high level synthesis
  5. reconfigurable system
  6. synthesis

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  • (2016)“Multi-Circuit”: Automatic Generation of an Application Specific Configurable Core for Known Set of Application CircuitsJournal of Circuits, Systems and Computers10.1142/S021812661650102425:09(1650102)Online publication date: Sep-2016
  • (2014)A top-down optimization methodology for mutually exclusive applicationsInternational Journal of Reconfigurable Computing10.1155/2014/8276132014(3-3)Online publication date: 1-Jan-2014
  • (2012)On the asymptotic costs of multiplexer-based reconfigurabilityProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228503(790-795)Online publication date: 3-Jun-2012
  • (2012)Efficient datapath merging for the overhead reduction of run-time reconfigurable systemsThe Journal of Supercomputing10.1007/s11227-010-0458-359:2(636-657)Online publication date: 1-Feb-2012
  • (2011)Flexibility and Reusability in the Digital Front-End of Cognitive Radio TerminalsCircuits, Systems, and Signal Processing10.1007/s00034-011-9306-930:4(799-821)Online publication date: 1-Aug-2011
  • (2010)High-level synthesis for designing multimode architecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.206275129:11(1736-1749)Online publication date: 1-Nov-2010
  • (2010)A modified merging approach for datapath configuration time reductionProceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications10.1007/978-3-642-12133-3_29(318-328)Online publication date: 17-Mar-2010
  • (2009)High speed merged-datapath design for run-time reconfigurable systems2009 International Conference on Field-Programmable Technology10.1109/FPT.2009.5377678(339-343)Online publication date: Dec-2009
  • (2009)Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-pathsIntegration, the VLSI Journal10.1016/j.vlsi.2008.12.00342:4(486-503)Online publication date: 1-Sep-2009
  • (2007)A design flow dedicated to multi-mode architectures for DSP applicationsProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326199(604-611)Online publication date: 5-Nov-2007
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