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A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool

Published:02 April 2005Publication History

ABSTRACT

The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing instances to be located and signals to be routed in 3-D space. Wire resource prediction is important for fast and accurate interconnection planning in 3-D FPGA. In this paper, we extend the existing analytic model shown in [13] with a new parameter for our 3-D FPGA which has cluster-based logic blocks. The proposed wire resource prediction model is applied to our 3-D FPGA using a Xilinx Virtex2 slice [18] and our 3-D routing architecture. We validate the effectiveness of the extended model by comparing the required number of channel wires predicted by the extended analytic equation with that of the placed and routed results using 3-D placement and routing algorithm designed for our 3-D FPGA for a number of benchmark circuits. The extended 3-D wire resource prediction model predicts the required channel capacity with an average of 11.1% error for 17 large circuits from LGSynth93 and ISPD2001 Verilog benchmarks.

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          cover image ACM Conferences
          SLIP '05: Proceedings of the 2005 international workshop on System level interconnect prediction
          April 2005
          114 pages
          ISBN:1595930337
          DOI:10.1145/1053355

          Copyright © 2005 ACM

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          Publication History

          • Published: 2 April 2005

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