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A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool

Published: 02 April 2005 Publication History

Abstract

The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing instances to be located and signals to be routed in 3-D space. Wire resource prediction is important for fast and accurate interconnection planning in 3-D FPGA. In this paper, we extend the existing analytic model shown in [13] with a new parameter for our 3-D FPGA which has cluster-based logic blocks. The proposed wire resource prediction model is applied to our 3-D FPGA using a Xilinx Virtex2 slice [18] and our 3-D routing architecture. We validate the effectiveness of the extended model by comparing the required number of channel wires predicted by the extended analytic equation with that of the placed and routed results using 3-D placement and routing algorithm designed for our 3-D FPGA for a number of benchmark circuits. The extended 3-D wire resource prediction model predicts the required channel capacity with an average of 11.1% error for 17 large circuits from LGSynth93 and ISPD2001 Verilog benchmarks.

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Cited By

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  • (2018)Advanced Devices and ArchitecturesPrinciples and Structures of FPGAs10.1007/978-981-13-0824-6_8(207-231)Online publication date: 4-Sep-2018
  • (2015)Three-Dimensional FPGAs: Configuration and CAD DevelopmentThree-Dimensional Design Methodologies for Tree-based FPGA Architecture10.1007/978-3-319-19174-4_5(95-116)Online publication date: 26-Jun-2015
  • (2010)Wirelength-driven force-directed 3D FPGA placementProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785582(435-440)Online publication date: 16-May-2010
  • Show More Cited By

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cover image ACM Conferences
SLIP '05: Proceedings of the 2005 international workshop on System level interconnect prediction
April 2005
114 pages
ISBN:1595930337
DOI:10.1145/1053355
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 02 April 2005

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Author Tags

  1. 3-D FPGA
  2. wire resource prediction

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SLIP05
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SLIP05: International Workshop on System Level Interconnect Prediction
April 2 - 3, 2005
California, San Francisco, USA

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Overall Acceptance Rate 6 of 8 submissions, 75%

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Cited By

View all
  • (2018)Advanced Devices and ArchitecturesPrinciples and Structures of FPGAs10.1007/978-981-13-0824-6_8(207-231)Online publication date: 4-Sep-2018
  • (2015)Three-Dimensional FPGAs: Configuration and CAD DevelopmentThree-Dimensional Design Methodologies for Tree-based FPGA Architecture10.1007/978-3-319-19174-4_5(95-116)Online publication date: 26-Jun-2015
  • (2010)Wirelength-driven force-directed 3D FPGA placementProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785582(435-440)Online publication date: 16-May-2010
  • (2009)High-performance, cost-effective heterogeneous 3D FPGA architecturesProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531603(251-256)Online publication date: 10-May-2009
  • (2009)High-performance, cost-effective heterogeneous 3D FPGA architecturesProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1508128.1508203(286-286)Online publication date: 24-Feb-2009
  • (2008)Designing a 3-D FPGAIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200045616:7(882-893)Online publication date: 1-Jul-2008

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