Article

Floorplan assisted data rate enhancement through wire pipelining: a real assessment

Authors:

Mario R. Casu,

Luca MacchiaruloAuthors Info & Claims

ISPD '05: Proceedings of the 2005 international symposium on Physical design

Pages 121 - 128

https://doi.org/10.1145/1055137.1055163

Published: 03 April 2005 Publication History

Get Access

Abstract

The recent shift towards wire pipelining (WP) mandated by technological factors has attracted attention towards latency-controlled floorplanning. However, no systematic study has been published so far that takes into account block and logic delay limitations. The present workaims at filling the gap by showing that blockdelay can limit and possibly prevent any real gain WP might promise. Recurring to adaptive WP schemes, on the other hand, allows relevant gains. We built floorplanner that optimizes for maximum data rate, taking into account various models of block delay, and compares them to the optimal results obtained when no wire pipelining is employed. Experiments with suitable floorplanning benchmarks and case studies are performed to substantiate theoretical intuitions.

References

[1]

The International Technology Roadmap for Semiconductors (ITRS), 2003, SIA.

Google Scholar

[2]

M.R. Casu and L. Macchiarulo, "Floorplanning for Throughput," Proc. ISPD'04.

Digital Library

Google Scholar

[3]

M. Ekpanyapong et al., "Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design," Proc. DAC 04, June 2004, San Diego CA.

Digital Library

Google Scholar

[4]

C. Long et al., "Floorplanning Optimization with Trajectory Piecewise-Linear Model for Pipelined Interconnects," Proc. DAC 04, June 2004, San Diego CA.

Digital Library

Google Scholar

[5]

L.P. Carloni et al ii, A Methodology for "Correct-by-Construction" Latency Insensitive Design", Proc. ICCAD 99, pp. 309--315.

Digital Library

Google Scholar

[6]

L.P. Carloni and A.L. Sangiovanni-Vincentelli, Performance Analysis and Optimization of Latency Insensitive Protocols, Proc. DAC 00, pp. 361--367.

Digital Library

Google Scholar

[7]

M. Singh and M. Theobald, Generalized Latency Insensitive Systems for Single-Clockand Multi-Clock Architectures, Proc. DATE 2004 Pris.

Digital Library

Google Scholar

[8]

http://vlsicad.eecs.umich.edu/BK/parquet/

Google Scholar

[9]

M. Iked et. al., A Hardware/Software Concurrent Design for Real-Time SP@ML MPEG2 Video-Encoder Chip Set, Proc. European Design and Test Conf., pp. 320--326, March 1996.

Digital Library

Google Scholar

Cited By

View all

Carloni L(2015)From Latency-Insensitive Design to Communication-Based System-Level DesignProceedings of the IEEE10.1109/JPROC.2015.2480849103:11(2133-2151)Online publication date: Nov-2015
https://doi.org/10.1109/JPROC.2015.2480849
Long CSimonson LLiao WHe L(2007)Microarchitecture configurations and floorplanning co-optimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89924015:7(830-841)Online publication date: 1-Jul-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.899240
Casu MMacchiarulo L(2006)Floorplanning With Wire Pipelining in Adaptive Communication ChannelsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88259025:12(2996-3004)Online publication date: 1-Dec-2006
https://dl.acm.org/doi/10.1109/TCAD.2006.882590

Index Terms

Floorplan assisted data rate enhancement through wire pipelining: a real assessment
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
2. Human-centered computing

Recommendations

Throughput-driven floorplanning with wire pipelining

The size of future high-performance SoC is such that the time-of-flight of wires connecting distant pins in the layout can be much higher than the clock period. In order to keep the frequency as high as possible, the wires may be pipelined. However, the ...
Floorplanning for throughput
ISPD '04: Proceedings of the 2004 international symposium on Physical design

Large Systems-on-Chip (SoC) in advanced technologies run at such high frequencies that the time-of-flight of signals connecting two distant pins in the layout can be higher than the clock period. In order to avoid performance penalties wires are ...
An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs

In this article we propose an effective algorithm flow to handle modern large-scale mixed-size placement, both with and without geometry constraints. The basic idea is to use floorplanning to guide the placement of objects at the global level. The flow ...

Comments

Information & Contributors

Information

Published In

ISPD '05: Proceedings of the 2005 international symposium on Physical design

April 2005

258 pages

ISBN:1595930213

DOI:10.1145/1055137

General Chair:
Patrick Groeneveld
Eindhoven University
,
Program Chair:
Lou Scheffer
Cadence

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 April 2005

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

ISPD05

Sponsor:

ISPD05: International Symposium on Physical Design 2005

April 3 - 6, 2005

California, San Francisco, USA

Acceptance Rates

Overall Acceptance Rate 62 of 172 submissions, 36%

Upcoming Conference

ISPD '25

Sponsor:
sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
180
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 05 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Carloni L(2015)From Latency-Insensitive Design to Communication-Based System-Level DesignProceedings of the IEEE10.1109/JPROC.2015.2480849103:11(2133-2151)Online publication date: Nov-2015
https://doi.org/10.1109/JPROC.2015.2480849
Long CSimonson LLiao WHe L(2007)Microarchitecture configurations and floorplanning co-optimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89924015:7(830-841)Online publication date: 1-Jul-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.899240
Casu MMacchiarulo L(2006)Floorplanning With Wire Pipelining in Adaptive Communication ChannelsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88259025:12(2996-3004)Online publication date: 1-Dec-2006
https://dl.acm.org/doi/10.1109/TCAD.2006.882590

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Throughput-driven floorplanning with wire pipelining

Floorplanning for throughput

An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations