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APlace: a general analytic placement framework

Published: 03 April 2005 Publication History

Abstract

We streamline and extend APlace, the general analytic placement engine based on ideas of Naylor et al. [7] and described in [3, 4, 5]. Previous work explored the adaptability of APlace to multiple contexts with good quality of results. For example, the framework was extended to traditional wirelength-driven standard-cell placement in [3, 5], achieving good results in placed HPWL and routed final wire-length. The framework was also extended to top-down multilevel placement, congestion-directed placement, mixed-size placement, timing-driven placement, I/O-core co-placement and constraint handling for mixed-signal contexts [3, 4, 5]. In this work, we have modified the implementation of APlace for speed and scalability. Improvements have been made in clustering, legalization and detailed placement strategies, as well as via a distributable solution framework for both global and detailed placement phases.

References

[1]
J. Gu and X. Huang, "Efficient Local Search with Search Space Smoothing: A Case Study of the Traveling Salesman Problem (TSP)", IEEE Trans. Systems, Man and Cybernetics 24(5) (1994), pp. 728--735.
[2]
D. Hill, "Method and System for High Speed Detailed Placement of Cells within an Integrated Circuit Design", US Patent 6370673, April 2002.
[3]
A. B. Kahng and Q. Wang, "Implementation and Extensibility of an Analytic Placer", Proc. Int. Symp. Physical Design, 2004, pp. 18--25.
[4]
A. B. Kahng and Q. Wang, "An Analytic Placer for Mixed-Size Placement and Timing-Driven Placement", Proc. Int. Conf. Computer Aided Design, 2004, 565--572.
[5]
A. B. Kahng and Q. Wang, "Implementation and Extensibility of an Analytic Placer", IEEE Trans. Computer Aided Design, to appear.
[6]
A. B. Kahng and X. Xu, "Accurate Pseudo-Constructive Wirelength and Congestion Estimation", Proc. ACM Int. Workshop on System-Level Interconnect Prediction, April 2003, pp. 61--68.
[7]
W. Naylor et al., "Non-Linear Optimization System and Method for Wire Length and Delay Optimization for an Automatic Electric Circuit Placer", US Patent 6301693, Oct. 2001.

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cover image ACM Conferences
ISPD '05: Proceedings of the 2005 international symposium on Physical design
April 2005
258 pages
ISBN:1595930213
DOI:10.1145/1055137
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 03 April 2005

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Author Tags

  1. analytical placement
  2. congestion
  3. mixed size
  4. multi-level

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ISPD05
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ISPD05: International Symposium on Physical Design 2005
April 3 - 6, 2005
California, San Francisco, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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  • (2024)A Hybrid ECO Detailed Placement Flow for Improved Reduction of Dynamic IR DropProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658727(390-396)Online publication date: 12-Jun-2024
  • (2024)Hierarchical reinforcement learning for chip-macro placement in integrated circuitPattern Recognition Letters10.1016/j.patrec.2024.02.002179(108-114)Online publication date: Mar-2024
  • (2023)ChiPFormerProceedings of the 40th International Conference on Machine Learning10.5555/3618408.3619165(18346-18364)Online publication date: 23-Jul-2023
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  • (2023)Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable ArraysIEEE Computer Architecture Letters10.1109/LCA.2023.326812622:1(45-48)Online publication date: 1-Jan-2023
  • (2022)Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC52403.2022.9712480(288-293)Online publication date: 17-Jan-2022
  • (2017)Physical Layout after Half a CenturyProceedings of the 2017 ACM on International Symposium on Physical Design10.1145/3036669.3038251(123-128)Online publication date: 19-Mar-2017
  • (2017)Search space reduction for the non-exact projective NPNP Boolean matching problem2017 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2017.8050970(1-4)Online publication date: May-2017
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