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PIM lite: a multithreaded processor-in-memory prototype

Published: 17 April 2005 Publication History

Abstract

PIM Lite is a processor-in-memory prototype implemented in a 0.18 micron logic process. PIM Lite provides a complete working demonstration of a minimal-state, lightweight multithreaded processor with low-overhead thread swapping. Minimizing processor state by keeping thread state in memory and using a regular, tiled and memory-centric design greatly simplified VLSI development and testing.

References

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J. Draper et al. The architecture of the DIVA processing-in-memory chip. In International Conference on Supercomputing, 2002.]]
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Y. Kang et al. FlexRAM: Toward an advanced intelligent memory system. In International Conference on Computer Design, 1999.]]
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K. Mai et al. Smart memories: A modular reconfigurable architecture. In ISCA, 2000.]]
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J. Brockman et al. A low cost, multithreaded processing-in-memory system. In Workshop on Memory Performance Issues, 2004.]]
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J. Brockman. PIM Lite architecture and assembly language manual. Technical report, University of Notre Dame CSE Dept., 2003.]]
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J. Brockman. Programming PIM Lite. Technical report, University of Notre Dame CSE Dept., 2003.]]
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W. Maly. IC design in the high-cost nanometer technologies era. In DAC, 2001.]]
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Shyamkumar Thoziyoor. PIM Lite: VLSI prototype of a multithreaded processor-in-memory chip. M.S. thesis, University of Notre Dame, 2004.]]
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S. Khatri et al. Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric. In ICCAD, 2000.]]
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L. Pileggi et al. Exploring regular fabrics to optimize the performance-cost trade-off. In DAC, 2000.]]
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Cited By

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  • (2020)The Non-Uniform Compute Device (NUCD) Architecture for Lightweight Accelerator Offload2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/PDP50117.2020.00013(38-45)Online publication date: Mar-2020
  • (2019)Multi-threading Semantics for Highly Heterogeneous Systems Using Mobile Threads2019 International Conference on High Performance Computing & Simulation (HPCS)10.1109/HPCS48598.2019.9188165(281-289)Online publication date: Jul-2019
  • (2017)A Case for Migrating Execution for Irregular ApplicationsProceedings of the Seventh Workshop on Irregular Applications: Architectures and Algorithms10.1145/3149704.3149770(1-8)Online publication date: 12-Nov-2017
  • Show More Cited By

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  1. PIM lite: a multithreaded processor-in-memory prototype

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    cover image ACM Conferences
    GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI
    April 2005
    518 pages
    ISBN:1595930574
    DOI:10.1145/1057661
    • General Chair:
    • John Lach,
    • Program Chairs:
    • Gang Qu,
    • Yehea Ismail
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 17 April 2005

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    Author Tags

    1. VLSI design
    2. multithreading
    3. processing-in-memory

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    GLSVLSI05
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    GLSVLSI05: Great Lakes Symposium on VLSI 2005
    April 17 - 19, 2005
    Illinois, Chicago, USA

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    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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    Cited By

    View all
    • (2020)The Non-Uniform Compute Device (NUCD) Architecture for Lightweight Accelerator Offload2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/PDP50117.2020.00013(38-45)Online publication date: Mar-2020
    • (2019)Multi-threading Semantics for Highly Heterogeneous Systems Using Mobile Threads2019 International Conference on High Performance Computing & Simulation (HPCS)10.1109/HPCS48598.2019.9188165(281-289)Online publication date: Jul-2019
    • (2017)A Case for Migrating Execution for Irregular ApplicationsProceedings of the Seventh Workshop on Irregular Applications: Architectures and Algorithms10.1145/3149704.3149770(1-8)Online publication date: 12-Nov-2017
    • (2016)Data-Centric Computing FrontiersProceedings of the Second International Symposium on Memory Systems10.1145/2989081.2989087(295-308)Online publication date: 3-Oct-2016
    • (2015)PIM-enabled instructionsACM SIGARCH Computer Architecture News10.1145/2872887.275038543:3S(336-348)Online publication date: 13-Jun-2015
    • (2015)PIM-enabled instructionsProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750385(336-348)Online publication date: 13-Jun-2015
    • (2010)Models for generating locality-tuned traveling threads for a hierarchical multi-level heterogeneous multicoreProceedings of the 7th ACM international conference on Computing frontiers10.1145/1787275.1787329(227-236)Online publication date: 17-May-2010
    • (2010)Modeling bounds on migration overhead for a traveling thread architecture2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)10.1109/IPDPSW.2010.5470686(1-8)Online publication date: Apr-2010

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