Article

Noise-tolerant high fan-in dynamic CMOS circuit design

Authors:

Walid Elgharbawy,

Pradeep Golconda,

Magdy BayoumiAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 134 - 137

https://doi.org/10.1145/1057661.1057694

Published: 17 April 2005 Publication History

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Abstract

Scaling CMOS technology to next generation improves performance, increases transistor density, and reduces power consumption per device. However, scaling also increases the subthreshold leakage current which greatly degrades the circuit's noise immunity. In this paper we propose a new circuit technique that makes domino dynamic CMOS more robust and more noise-tolerant with minimal performance degradation and energy overhead. Simulations for high fan-in gates show a noise immunity improvement of 2.13X using Berkeley Predictive Technology Models (BPTM) of 70nm with minimal performance and power degradations over standard domino circuits.

References

[1]

R. Kumar, "Interconnect and Noise Immunity Design for the Pentium 4 Processor," Intel Technology Journal, Q1 2001 Issue, Feb. 2001.

Google Scholar

[2]

M. W. Allam, M. H. Anis, and M. I. Elmasry, "High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies". In The International Symposium on Low Power Electronics and Design ISLPED, pages 155--160, 2000.

Digital Library

Google Scholar

[3]

A. Chandrakasan, W. J. Bowhill, and F. Fox, Design of High-Performance Microprocessor Circuits. Wiley-IEEE Press, 2000.

Digital Library

Google Scholar

[4]

V. De and S. Borkar, "Technology and design challenges for low power and high performance," Proc. Of Intl. Symp. on Low-Power Electronics and Design, pp. 163--168, San Diego, CA, August 1999.

Digital Library

Google Scholar

[5]

L. Wang, R. Krishnamurthy, K. Soumyanath and N.Shanbhag, "An Energy-Efficient Leakage-Tolerant Dynamic Circuit Techniques," Proc. of 2000 ASIC conference, pp221--225, 2000.

Google Scholar

[6]

Berkeley Predictive Technology Model (BPTM), http://www-device.eecs.Berkeley.edu/~ptm/

Google Scholar

[7]

Y. Ye, S. Borkar, and V. De, "New technique for standby leakage reduction in high-performance circuits," in Dig. Tech. Papers Symp. VLSI Circuits, 1998, pp. 40--41.

Google Scholar

[8]

A. Alvandpour, R.K. Krishnamurthy, K. Soumyanath, S.Y. Borkar, A sub-130-nm conditional keeper technique IEEE Journal of Solid-State Circuits, Volume: 37, Issue: 5, May 2002 Pages: 633--638.

Crossref

Google Scholar

[9]

H. Mahmoodi-Meimand, K. Roy, "Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style," IEEE Transactions on Circuits and Systems I Volume: 51, Issue: 3, March 2004 Pages: 495--503.

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Cited By

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Angeline ABhaaskaran V(2021)Domino Logic Keeper Circuit Design Techniques: A ReviewJournal of The Institution of Engineers (India): Series B10.1007/s40031-021-00668-5103:2(669-679)Online publication date: 9-Sep-2021
https://doi.org/10.1007/s40031-021-00668-5
Parashar SKumar CPattanaik M(2011)An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise ToleranceProceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2011.31(49-53)Online publication date: 4-Jul-2011
https://dl.acm.org/doi/10.1109/ISVLSI.2011.31
Pattanaik MParashar SKumar CChouhan AMahor V(2011)A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design TechniqueProceedings of the 2011 International Symposium on Electronic System Design10.1109/ISED.2011.59(118-123)Online publication date: 19-Dec-2011
https://dl.acm.org/doi/10.1109/ISED.2011.59
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Index Terms

Noise-tolerant high fan-in dynamic CMOS circuit design
1. Hardware
  1. Very large scale integration design

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Published In

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 17 April 2005

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

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Angeline ABhaaskaran V(2021)Domino Logic Keeper Circuit Design Techniques: A ReviewJournal of The Institution of Engineers (India): Series B10.1007/s40031-021-00668-5103:2(669-679)Online publication date: 9-Sep-2021
https://doi.org/10.1007/s40031-021-00668-5
Parashar SKumar CPattanaik M(2011)An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise ToleranceProceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2011.31(49-53)Online publication date: 4-Jul-2011
https://dl.acm.org/doi/10.1109/ISVLSI.2011.31
Pattanaik MParashar SKumar CChouhan AMahor V(2011)A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design TechniqueProceedings of the 2011 International Symposium on Electronic System Design10.1109/ISED.2011.59(118-123)Online publication date: 19-Dec-2011
https://dl.acm.org/doi/10.1109/ISED.2011.59
Jinhui Wang Wuchen Wu Na Gong Ligang Hou (2010)Domino gate with modified voltage keeper2010 11th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2010.5450538(443-446)Online publication date: Mar-2010
https://doi.org/10.1109/ISQED.2010.5450538
Pattanaik MKhan FVaraprasad M(2010)Improvement of noise tolerance analysis in deep-submicron low voltage dynamic CMOS logic circuits2010 International Conference on Electronic Devices, Systems and Applications10.1109/ICEDSA.2010.5503105(48-53)Online publication date: Apr-2010
https://doi.org/10.1109/ICEDSA.2010.5503105
Mazumdar KPattanaik MPrakash R(2009)Novel low power noise tolerant dynamic circuit design techniqueTENCON 2009 - 2009 IEEE Region 10 Conference10.1109/TENCON.2009.5396245(1-5)Online publication date: Nov-2009
https://doi.org/10.1109/TENCON.2009.5396245
Mazumdar KPattanaik M(2009)Noise tolerance enhancement in low voltage dynamic circuits2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems10.1109/ELECTRO.2009.5441166(84-87)Online publication date: Dec-2009
https://doi.org/10.1109/ELECTRO.2009.5441166
Mazumdar KPattanaik M(2009)Noise tolerance enhancement in low voltage dynamic circuits2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era10.1109/DTIS.2009.4938017(23-27)Online publication date: Apr-2009
https://doi.org/10.1109/DTIS.2009.4938017
Na GJinhui WBaozeng GYongqing WXiaobing CXiuli T(2009)Robustness aware high performance high fan-in domino OR logic designJournal of Semiconductors10.1088/1674-4926/30/6/06500530:6(065005)Online publication date: 24-Jun-2009
https://doi.org/10.1088/1674-4926/30/6/065005

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Abstract

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Recommendations

On circuit techniques to improve noise immunity of CMOS dynamic logic

Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit

Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile

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