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Noise aware behavioral modeling of the Ε-Δ fractional-N frequency synthesizer

Published: 17 April 2005 Publication History

Abstract

This paper presents the behavioral model of a Ε-Δ fractional-N frequency synthesizer in terms of different noise sources and non-ideal effects. To accurately predict the phase noise of the synthesizer, different jitter noise sources such as phase modulation (PM) noise in phase-frequency detector and divider, frequency modulation (FM) noise in VCO are properly depicted. The Ε-Δ modulator, with its divider value dithered and quantization noise dynamically injected to the PLL, is described in behavioral model, which allows the designer to study the quantization noise impaction to the PLL phase noise. All the models are implemented in VHDL-AMS and simulated using Mentor Graphics ADvance-MS (ADMS). Our behavioral modeling method enables a fast simulation of the PLL system and an accurate phase noise prediction.

References

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T.A. Riley, M. A. Copeland. Delta-Sigma Modulation in Fractional-N Frequency Synthesis. In IEEE J. Solid State Circuits, vol. 28, pp. 553--559, May 1993.
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A. Demir, E. Liu, A. L. S. Vincertelli and I. Vassiliou. Behavioral Simulation Techniques for Phase/Delay-locked Systems. In IEEE Custom Integrated Circuits Conference, pp. 453--456, 1994.
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M. Hinz, I. Konenkamp and E.H. Horneber. Behavioral Modeling and Simulation of Phase-Locked Loops for RF Front Ends. In IEEE Midwest Symp. On Circuits and Systems, pp. 194--197, Aug. 2000.
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M. H. Perrott, M.D. Trott, and C. G. Sodini. A Modeling Approach for Ε-Δ Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis. In IEEE Journal of Solid-State Circuits, Vol. 37, No. 8, pp. 1028--1038, Aug. 2002.
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K. S. Kundert. Modeling and Simulation of Jitter in Phase-Locked Loops. Cadence Design Systems. San Jose, California, USA.
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B. Millter and R.J. Conley. A Multiple Modulator Fractional Divider. In IEEE Transactions on Instrumentation and Measurement. Vol. 40, No. 3, 578--583, Jun 1991.
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I. Galton. Delta-Sigma Data Conversion in Wireless Transceivers. In IEEE Transactions on Microwave Theory and Techniques, Vol. 50, no. 1, pp. 302--316, Jan 2002.
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S. Norsworthy, R. Schreier, and G. Temes. Delta-Sigma Data Converters: Theory, Design, and Simulation. New York: IEEE Press, 1997.
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Cited By

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  • (2012)S-? Fractional-N Phase-Locked Loop Design Using HDL and Transistor-Level Models for Wireless CommunicationsWireless Radio-Frequency Standards and System Design10.4018/978-1-4666-0083-6.ch005(99-118)Online publication date: 2012
  • (2009)A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral levelProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509755(516-521)Online publication date: 19-Jan-2009
  • (2008)A straightforward ΣΔ fractional-N phase-locked loop HDL design for RF applicationsProceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics10.5555/1415563.1415581(84-88)Online publication date: 27-May-2008
  • Show More Cited By

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  1. Noise aware behavioral modeling of the Ε-Δ fractional-N frequency synthesizer

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    cover image ACM Conferences
    GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI
    April 2005
    518 pages
    ISBN:1595930574
    DOI:10.1145/1057661
    • General Chair:
    • John Lach,
    • Program Chairs:
    • Gang Qu,
    • Yehea Ismail
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 17 April 2005

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    Author Tags

    1. PLL
    2. frequency synthesizer
    3. jitter noise
    4. phase noise

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    April 17 - 19, 2005
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    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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    View all
    • (2012)S-? Fractional-N Phase-Locked Loop Design Using HDL and Transistor-Level Models for Wireless CommunicationsWireless Radio-Frequency Standards and System Design10.4018/978-1-4666-0083-6.ch005(99-118)Online publication date: 2012
    • (2009)A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral levelProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509755(516-521)Online publication date: 19-Jan-2009
    • (2008)A straightforward ΣΔ fractional-N phase-locked loop HDL design for RF applicationsProceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics10.5555/1415563.1415581(84-88)Online publication date: 27-May-2008
    • (2008)Systematic HDL Design of a S-? Fractional-N Phase-Locked Loop for Wireless Applications2008 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2008.40(173-178)Online publication date: Apr-2008

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