Cited By
View all- Pasricha SDutt N(2008)Custom Bus-Based On-Chip Communication Architecture DesignOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00008-6(301-340)Online publication date: 2008
In this paper, a novel asynchronous layered interface for a high performance on-chip bus is designed in a Globally Asynchronous Locally Synchronous (GALS) style. The proposed asynchronous layered interface with distributed and modularized control ...
Power consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous network-on-chip ...
The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the ...
Association for Computing Machinery
New York, NY, United States
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in