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High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion

Published: 17 April 2005 Publication History

Abstract

In this paper, we propose a high performance asynchronous on-chip bus with multiple issue and in-order/out-of-order completion for a Globally Asynchronous Locally Synchronous (GALS) design. The proposed bus implementation can be characterized with distributed and modularized control units based on a layered architecture to support multiple issue and in-order/out-of-order completion. Simulation results reveal that throughputs of asynchronous on-chip buses with multiple issue and in-order/out-of-order completion increases by 31.3% / 34.3%, while power consumption overhead is only 6.76% / 3.98% respectively, compared to a simple asynchronous on-chip bus with only a single issue feature.

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J. Bainbridge, Asynchronous system-on-chip interconnect. Ph.D. thesis, The University of Manchester, UK, 2000.
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E.-G. Jung, B.-S. Choi, and D.-I. Lee High performance asynchronous bus for SoC. In Proc. ISCAS, 2003, V-505-V-508.
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E. Salminen, V. Lahtinen, K. Kuusilinna, and T. Hamalainen Overview of bus-based system-on-chip interconnections. In Proc. ISCAS, 2002, II-372-II-375.
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E.-S.Kim, J.-G. Lee, D.-I. Lee Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis. In Proc. ASYNC, 2000, 104--105.
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    cover image ACM Conferences
    GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI
    April 2005
    518 pages
    ISBN:1595930574
    DOI:10.1145/1057661
    • General Chair:
    • John Lach,
    • Program Chairs:
    • Gang Qu,
    • Yehea Ismail
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    Publication History

    Published: 17 April 2005

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    Author Tags

    1. GALS
    2. SoC
    3. asynchronous on-chip bus
    4. in-order completion
    5. multiple issue
    6. out-of-order completion

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    GLSVLSI05: Great Lakes Symposium on VLSI 2005
    April 17 - 19, 2005
    Illinois, Chicago, USA

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