skip to main content
10.1145/1057661.1057722acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

An effective and efficient ATPG-based combinational equivalence checker

Published:17 April 2005Publication History

ABSTRACT

An effective and efficient ATPG-based combinational equivalence checker.

References

  1. R. Arora and M. Hsiao. Enhancing sat-based equivalence checking with static logic implications. In Proc. High-Level Design Validation and Test Workshop, pages 12--14, November 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. C. Berman and L. Trevillyan. Functional comparison of logic designs for vlsi circuits. In Proc. International Conference on Computer-Aided Design, pages 456--459, November 1989.Google ScholarGoogle ScholarCross RefCross Ref
  3. D. Brand. Verification of large synthesized designs. In Proc. International Conference on Computer-Aided Design, pages 534--537, November 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. R. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, 35(8):677--691, August 1986. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. J. Burch and V. Singhal. Tight integration of combinational verification methods. In Proc. International Conference on Computer-Aided Design, pages 570--576, November 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. P. Goel and B. Rosales. Podem-x: An automatic test generation system for vlsi logic structures. In Proc. Design Automation Conference, pages 260--268, June 1981. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. E. Goldberg and Y. Novikov. Berkmin: a fast and robust sat-solver. In Proc. Design, Automation and Test in Europe Conference, pages 142--149, March 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. E. Goldberg, M. Prasad, and R. Brayton. Using sat for combinational equivalence checking. In Proc. Design, Automation and Test in Europe Conference, pages 114--121, March 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. L. Goldstein and E. Thigpen. Scoap: Sandia controllability/observability analysis program. In Proc. Design Automation Conference, pages 190--196, June 1980. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. A. Kuehlmann and F. Krohm. Equivalence checking using cuts and heaps. In Proc. Design Automation Conference, pages 263--268, June 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. W. Kunz. Hannibal: An efficient tool for logic verification based on recursive learning. In Proc. International Conference on Computer-Aided Design, pages 538--543, November 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. F. Lu, L. Wang, K. Cheng, and R. Huang. A circuit sat solver with signal correlation guided learning. In Proc. Design, Automation and Test in Europe Conference, pages 892--897, March 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. J. P. Marques-Silva and K. A. Sakallah. Grasp: A search algorithm for propositional satisfiability. IEEE Transactions on Computers, 48(5):506--521, May 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Y. Matsunaga. An efficient equivalence checker for combinational circuits. In Proc. Design Automation Conference, pages 629--634, June 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient sat solver. In Proc. Design Automation Conference, pages 629--634, June 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. S. Reda and A. Salem. Combinational equivalence checking using boolean satisfiability and binary decision diagrams. In Proc. Design, Automation and Test in Europe Conference, pages 122--126, March 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. S. Reda, A. Wahba, and A. Salem. M-check: A multiple engine combinational equivalence checker. In Proc. International Symposium on Circuits and Systems, pages 613--616, May 2000.Google ScholarGoogle ScholarCross RefCross Ref
  18. S. Reddy, W. Kunz, and D. Pradhan. Novel verification framework combining structural and obdd methods in a synthesis environment. In Proc. Design Automation Conference, pages 414--419, June 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. J. Roth. Diagnosis of automata failures: A calculus and a method. IBM Journal of Research and Development, 10:278--291, July 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. E. Sentovich, K. Singh, C. Moon, H. Savoj, R. Brayton, and A. Sangiovanni-Vincentelli. Sequential circuit design using synthesis and optimization. In Proc. International Conference on Computer Design, pages 328--333, October 1992. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. C. Weng, S. Reddy, I. Pomeranz, X. Lin, and J.Rajski. Conflict driven techniques for improving deterministic test pattern generation. In Proc. International Conference on Computer-Aided Design, pages 87--93, November 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. An effective and efficient ATPG-based combinational equivalence checker

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in
    • Published in

      cover image ACM Conferences
      GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI
      April 2005
      518 pages
      ISBN:1595930574
      DOI:10.1145/1057661
      • General Chair:
      • John Lach,
      • Program Chairs:
      • Gang Qu,
      • Yehea Ismail

      Copyright © 2005 ACM

      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 17 April 2005

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • Article

      Acceptance Rates

      Overall Acceptance Rate312of1,156submissions,27%

      Upcoming Conference

      GLSVLSI '24
      Great Lakes Symposium on VLSI 2024
      June 12 - 14, 2024
      Clearwater , FL , USA

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader