ABSTRACT
An effective and efficient ATPG-based combinational equivalence checker.
- R. Arora and M. Hsiao. Enhancing sat-based equivalence checking with static logic implications. In Proc. High-Level Design Validation and Test Workshop, pages 12--14, November 2003. Google ScholarDigital Library
- C. Berman and L. Trevillyan. Functional comparison of logic designs for vlsi circuits. In Proc. International Conference on Computer-Aided Design, pages 456--459, November 1989.Google ScholarCross Ref
- D. Brand. Verification of large synthesized designs. In Proc. International Conference on Computer-Aided Design, pages 534--537, November 1993. Google ScholarDigital Library
- R. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, 35(8):677--691, August 1986. Google ScholarDigital Library
- J. Burch and V. Singhal. Tight integration of combinational verification methods. In Proc. International Conference on Computer-Aided Design, pages 570--576, November 1998. Google ScholarDigital Library
- P. Goel and B. Rosales. Podem-x: An automatic test generation system for vlsi logic structures. In Proc. Design Automation Conference, pages 260--268, June 1981. Google ScholarDigital Library
- E. Goldberg and Y. Novikov. Berkmin: a fast and robust sat-solver. In Proc. Design, Automation and Test in Europe Conference, pages 142--149, March 2002. Google ScholarDigital Library
- E. Goldberg, M. Prasad, and R. Brayton. Using sat for combinational equivalence checking. In Proc. Design, Automation and Test in Europe Conference, pages 114--121, March 2001. Google ScholarDigital Library
- L. Goldstein and E. Thigpen. Scoap: Sandia controllability/observability analysis program. In Proc. Design Automation Conference, pages 190--196, June 1980. Google ScholarDigital Library
- A. Kuehlmann and F. Krohm. Equivalence checking using cuts and heaps. In Proc. Design Automation Conference, pages 263--268, June 1997. Google ScholarDigital Library
- W. Kunz. Hannibal: An efficient tool for logic verification based on recursive learning. In Proc. International Conference on Computer-Aided Design, pages 538--543, November 1993. Google ScholarDigital Library
- F. Lu, L. Wang, K. Cheng, and R. Huang. A circuit sat solver with signal correlation guided learning. In Proc. Design, Automation and Test in Europe Conference, pages 892--897, March 2003. Google ScholarDigital Library
- J. P. Marques-Silva and K. A. Sakallah. Grasp: A search algorithm for propositional satisfiability. IEEE Transactions on Computers, 48(5):506--521, May 1999. Google ScholarDigital Library
- Y. Matsunaga. An efficient equivalence checker for combinational circuits. In Proc. Design Automation Conference, pages 629--634, June 1996. Google ScholarDigital Library
- M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient sat solver. In Proc. Design Automation Conference, pages 629--634, June 2001. Google ScholarDigital Library
- S. Reda and A. Salem. Combinational equivalence checking using boolean satisfiability and binary decision diagrams. In Proc. Design, Automation and Test in Europe Conference, pages 122--126, March 2001. Google ScholarDigital Library
- S. Reda, A. Wahba, and A. Salem. M-check: A multiple engine combinational equivalence checker. In Proc. International Symposium on Circuits and Systems, pages 613--616, May 2000.Google ScholarCross Ref
- S. Reddy, W. Kunz, and D. Pradhan. Novel verification framework combining structural and obdd methods in a synthesis environment. In Proc. Design Automation Conference, pages 414--419, June 1995. Google ScholarDigital Library
- J. Roth. Diagnosis of automata failures: A calculus and a method. IBM Journal of Research and Development, 10:278--291, July 1996. Google ScholarDigital Library
- E. Sentovich, K. Singh, C. Moon, H. Savoj, R. Brayton, and A. Sangiovanni-Vincentelli. Sequential circuit design using synthesis and optimization. In Proc. International Conference on Computer Design, pages 328--333, October 1992. Google ScholarDigital Library
- C. Weng, S. Reddy, I. Pomeranz, X. Lin, and J.Rajski. Conflict driven techniques for improving deterministic test pattern generation. In Proc. International Conference on Computer-Aided Design, pages 87--93, November 2002. Google ScholarDigital Library
Index Terms
- An effective and efficient ATPG-based combinational equivalence checker
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