Abhishek Mitra
ABSTRACT
Embedded software is a preferred choice for implementing system functionality in modern System-on-Chip (SoC) designs, due to the high flexibility, and lower engineering costs provided by software over hardware. With continuous improvements in embedded processor performance, many system functions, which have traditionally been implemented using dedicated hardware (such as those with real-time performance requirements), are becoming potential candidates for software implementation. For complex SoCs containing many different components, identifying such functions (or hardware blocks), and re-implementing them as embedded software, is a labor-intensive, manual, and error-prone process. In this paper we present techniques for the transformation of behaviors of selected hardware blocks into equivalent software implementations. In particular, we describe Softenit, a methodology for "softening" of SoC hardware, that takes as input, a partitioned and mapped system description, and generates a modified system architecture in which the fraction of system functionality implemented using embedded software is significantly boosted. Application of this methodology to an IEEE 802.11 MAC processor design demonstrates that it can be used to generate new, "softened" system architectures, that yield large reductions in hardware complexity, while satisfying performance requirements, at very low computational cost.
- J. Edney and W. A. Arbaugh, Real 802.11 Security: Wi-Fi Protected Access and 802.11i. Addison Wesley, 2003. Google Scholar
Digital Library
- "Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications (Chapter 8)." IEEE Computer Society LAN/MAN Standards Committee, IEEE Std 802.11-1999 Edition.Google Scholar
- D. Gajski, F. Vahid, S. Narayan, and J. Gong, Specification and Design of Embedded Systems. Prentice Hall, 1994. Google ScholarDigital Library
- F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jureska, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, E. Sentovich, K. Suzuki, and B. Tabbara, Hardware-software Co-Design of Embedded Systems: The POLIS Approach. Kluwer Academic Publishers, Norwell, MA., 1997. Google ScholarDigital Library
- A. Kalavade and E. Lee, "A hardware-software codesign methodology for DSP applications," IEEE Design and Test of Computers, vol. 10, pp. 16--28, Sep. 1993. Google ScholarDigital Library
- R.Ernst, J.Henkel, and T.Benner, "Hardware-software cosynthesis for microcontrollers," IEEE Design & Test of Computers, pp. 64--75, Dec. 1993. Google ScholarDigital Library
- R. K. Gupta and G. Micheli, "Hardware/Software Co-synthesis for Digital Systems," pp. 29--41, Sep. 1993. Google ScholarDigital Library
- T. J. Callahan, J. R. Hauser, and J. Wawrzynek, "The Garp Architecture and C Compiler," IEEE Computer, vol. 33, pp. 62--69, Apr. 2000. Google ScholarDigital Library
- http://www.tensilica.com.Google Scholar
- http://www.synfora.com.Google Scholar
- http://www.criticalblue.com.Google Scholar
- G. Stitt, F. Vahid, and S. Nemetebaksh, "Energy Savings and Speedups from Partitioning Critical Software Loops to Hardware in Embedded Systems," IEEE Trans. Embedded Computer Systems, vol. 03, pp. 218--232, Feb. 2004. Google ScholarDigital Library
- http://www.systemc.org.Google Scholar
- http://www.systemverilog.org.Google Scholar
- K. Wakabayashi and T. Okamoto, "C-Based SoC Design Flow and EDA Tools: An ASIC and System Vendor Perspective," IEEE Trans. Computer-Aided Design, vol. 19, pp. 1507--1522, Dec. 2000. Google ScholarDigital Library
- http://www.necel.com/micro/english/v850/product/index.html.Google Scholar
- http://www.synopsys.com/products/logic/.Google Scholar
- http://www.necel.com/cbic/en/product/cb12.html.Google Scholar
Index Terms
- SOFTENIT: a methodology for boosting the software content of system-on-chip designs
Recommendations
Hardware/software partitioning of operating systems: a behavioral synthesis approach
GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSIIn this paper we propose a hardware real time operating system(HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the POSIX layer of a general purpose RTOS for implementing task synchronization ...
Hardware/software optimization of error detection implementation for real-time embedded systems
CODES/ISSS '10: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesisThis paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant real-time distributed embedded systems used for safety-critical applications. An application is modeled as a set of processes ...
FPGA implementation of a HW/SW platform for multimedia embedded systems
This paper presents a HW/SW platform for embedded video system. It has been designed around an embedded RISC processor and FPGA technologies and provides video input and output interfaces. The configurable platform has been used to implement a real time ...
Comments