Article

1-V 7-mW dual-band fast-locked frequency synthesizer

Authors:

Vikas Sharma,

Chien-Liang Chen,

Chung-Ping ChenAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 431 - 435

https://doi.org/10.1145/1057661.1057764

Published: 17 April 2005 Publication History

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Abstract

This paper presents a fully integrated 1-V, dual band, fast-locked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 - 2.7 GHz with a step of 9.375 MHz, and in the range of 5.14 - 5.70 GHz with a step of 20 MHz. Simulation using 0.18-μm rf and mixed-signal CMOS technology demonstrates a total power consumption of 7-mW. An adaptive bandwidth controller is employed to achieve a fast locking time. The frequency divider combines the conventional and the extended true-single-phase-clock logics. To ensure a proper dividing function, a cascode voltage switch (CVS) topology is used in the preamplifier stage. The reference spurs at an offset of 10-MHz are as low as -80 dBc, and the phase noise at an offset of 1 MHz is lower than -118 dBc for the entire tuning range.

References

[1]

C.M. Hung and K.K.O, "A fully integrated 1.5-V 5.5 GHz CMOS phase-locked loop", in IEEE Journal of Solid-State Circuits, Vol. 37, pp. 521--525, Apr.2002.

Crossref

Google Scholar

[2]

B.U.H. Klepser, M. Scholz, and J. J. Kucera, "A 5.7-GHz HiPerLAN SiGe BiCMOS voltage-controlled oscillator and phase-locked-loop frequency synthesizer," in Radio-Frequency Integrated Circuits Symposium Dig., pp. 61--64, Phoenix, AZ, May 2001.

Google Scholar

[3]

H. R. Rategh, H. Samavati, and T. H. Lee, "A CMOS frequency synthesizer with an injected-locked frequency divider for a 5-GHz wireless LAN receiver," in IEEE Journal of Solid-State Circuits, Vol. 35, pp. 780--787, May 2000.

Crossref

Google Scholar

[4]

N. Krishnapura and P. R. Kinget, "A 5.3-GHz programmable divider for HiPerLAN in 0.25-͘m CMOS," in IEEE Journal of Solid State Circuits, Vol. 35, pp. 1019--1024, July 2000.

Crossref

Google Scholar

[5]

Wong, J.M.C., Cheung, V.S.L., and Luong, H.C., 'A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-͘m CMOS process', in IEEE Journal of Solid-State Circuits, Vol. 38(10), pp. 1643--1648, 2003.

Crossref

Google Scholar

[6]

S. Pellerano, and S. Levantino, "A 13.5-mW 5-GHz Frequency Synthesizer With Dynamic-Logic Frequency Divider," in IEEE Journal of Solid-State Circuits, Vol. 39, pp. 378--383, Feb. 2004.

Crossref

Google Scholar

[7]

Joonsuk Lee, and Beomsup Kim, "A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control," in IEEE Journal of Solid-State Circuits, Vol. 35, pp. 1137--1145, Feb. 2000.

Crossref

Google Scholar

[8]

Baki, R.A.; El-Gamal, M.N.; "A New CMOS Charge Pump for Low-Voltage(1V) High-Speed PLL Application," in Proceedings of International Symposium on Circuits and Systems ISCAS '03., Volume: 1, 25-28, pp. I-657--I-660, May 2003.

Google Scholar

[9]

Hajimiri, A.; Lee, T.H.; "Design issues in CMOS differential LC oscillators", in IEEE Journal of Solid-State Circuits, Vol. 34, Issue: 5 pp. 717--724, May 1999.

Crossref

Google Scholar

Cited By

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Liao DHung C(2010)A spur-reduction frequency synthesizer for WIMAX applicationsProceedings of 2010 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2010.5537089(2594-2597)Online publication date: May-2010
https://doi.org/10.1109/ISCAS.2010.5537089
Bazzazi ANabavi A(2009)Design of a low-power 10GHz frequency divider using Extended True Single Phase Clock (E-TSPC) logic2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems10.1109/ELECTRO.2009.5441145(173-176)Online publication date: Dec-2009
https://doi.org/10.1109/ELECTRO.2009.5441145
Pinping Sun Jaeyoung Jung Youngsik Kim Deukhyoun Heo Lanchuan Zhou (2008)An ultra low power analog frequency divider2008 IEEE MTT-S International Microwave Symposium Digest10.1109/MWSYM.2008.4633062(1489-1492)Online publication date: Jun-2008
https://doi.org/10.1109/MWSYM.2008.4633062
Show More Cited By

Index Terms

1-V 7-mW dual-band fast-locked frequency synthesizer
1. Hardware
  1. Integrated circuits

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Published In

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 17 April 2005

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April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Liao DHung C(2010)A spur-reduction frequency synthesizer for WIMAX applicationsProceedings of 2010 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2010.5537089(2594-2597)Online publication date: May-2010
https://doi.org/10.1109/ISCAS.2010.5537089
Bazzazi ANabavi A(2009)Design of a low-power 10GHz frequency divider using Extended True Single Phase Clock (E-TSPC) logic2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems10.1109/ELECTRO.2009.5441145(173-176)Online publication date: Dec-2009
https://doi.org/10.1109/ELECTRO.2009.5441145
Pinping Sun Jaeyoung Jung Youngsik Kim Deukhyoun Heo Lanchuan Zhou (2008)An ultra low power analog frequency divider2008 IEEE MTT-S International Microwave Symposium Digest10.1109/MWSYM.2008.4633062(1489-1492)Online publication date: Jun-2008
https://doi.org/10.1109/MWSYM.2008.4633062
Casha OGrech IGatt EMicallef J(2005)1.6-GHz low power low phase noise quadrature phase locked loop with on chip DC-DC converter for wide tuning range2005 12th IEEE International Conference on Electronics, Circuits and Systems10.1109/ICECS.2005.4633373(1-4)Online publication date: Dec-2005
https://doi.org/10.1109/ICECS.2005.4633373

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Recommendations

A 1.41---1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler

A monolithic sigma-delta fractional-N frequency synthesizer with implicit dual-path filter and phase switching multi-modulus frequency divider

A Ku-band dual control path frequency synthesizer using varactorless Q-enhanced LC-type VCO

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