article

A detailed power model for field-programmable gate arrays

Authors:

Kara K. W. Poon,

Steven J. E. Wilton,

Andy YanAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 10, Issue 2

Pages 279 - 302

https://doi.org/10.1145/1059876.1059881

Published: 01 April 2005 Publication History

Abstract

Power has become a critical issue for field-programmable gate array (FPGA) vendors. Understanding the power dissipation within FPGAs is the first step in developing power-efficient architectures and computer-aided design (CAD) tools for FPGAs. This article describes a detailed and flexible power model which has been integrated in the widely used Versatile Place and Route (VPR) CAD tool. This power model estimates the dynamic, short-circuit, and leakage power consumed by FPGAs. It is the first flexible power model developed to evaluate architectural tradeoffs and the efficiency of power-aware CAD tools for a variety of FPGA architectures, and is freely available for noncommercial use. The model is flexible, in that it can estimate the power for a wide variety of FPGA architectures, and it is fast, in that it does not require extensive simulation, meaning it can be used to explore a large architectural space. We show how the model can be used to investigate the impact of various architectural parameters on the energy consumed by the FPGA, focusing on the segment length, switch block topology, lookuptable size, and cluster size.

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Index Terms

A detailed power model for field-programmable gate arrays
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 10, Issue 2

April 2005

244 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1059876

Issue’s Table of Contents

Copyright © 2005 ACM.

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 April 2005

Published in TODAES Volume 10, Issue 2

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https://doi.org/10.1007/978-981-99-7755-0_2
Liu PZhang ZYin CChen LJiang JWang QMao ZJing N(2023)Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL60245.2023.00024(116-122)Online publication date: 4-Sep-2023
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Lu LLiang Y(2022)Morphling: A Reconfigurable Architecture for Tensor ComputationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313532241:11(4733-4746)Online publication date: 1-Nov-2022
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