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Controlling leakage power with the replacement policy in slumberous caches

Published: 04 May 2005 Publication History

Abstract

As technology scales down at an exponential rate, leakage power is fast becoming the dominant component of the total power budget. A large share of the total leakage power is dissipated in the cache hierarchy. To reduce cache leakage, individual cache lines can be kept in drowsy mode, a low voltage, low leakage state. Every cache access may then result in dynamic power consumption and performance penalties. A trade-off between the amount of leakage power saved on one hand, and the impact on dynamic power and performance on the other hand must be reachedTo affect this trade-off, we introduce "slumberous caches" in which the power level of cache lines is controlled with the cache replacement policy. In a slumberous cache, cache lines are maintained at different power save modes which we call "tranquility levels", which depend on their order of replacement priorities.We evaluate the trade-offs in the context of PLRU, a common cache replacement algorithm. We explore various assignments of the tranquility levels to lines and compare overall power and performance impacts. As technology scales down, the dynamic power required to energize slumberous cache lines drops drastically while the leakage power savings remain roughly steady. The performance penalty--in cycles-- remains constant with technology scaling for each scheme we evaluate.

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Cited By

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  • (2019)Exploring Adaptive Cache for Reconfigurable VLIW ProcessorIEEE Access10.1109/ACCESS.2019.29195897(72634-72646)Online publication date: 2019
  • (2014)A workload independent energy reduction strategy for D-NUCA cachesThe Journal of Supercomputing10.1007/s11227-013-1033-568:1(157-182)Online publication date: 1-Apr-2014
  • (2013)Leakage energy estimates for HPC applicationsProceedings of the 1st International Workshop on Energy Efficient Supercomputing10.1145/2536430.2536431(1-8)Online publication date: 17-Nov-2013
  • Show More Cited By

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    cover image ACM Conferences
    CF '05: Proceedings of the 2nd conference on Computing frontiers
    May 2005
    467 pages
    ISBN:1595930191
    DOI:10.1145/1062261
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 04 May 2005

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    Author Tags

    1. drowsy cache
    2. leakage power
    3. replacement policy
    4. tranquility level

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    CF05: Computing Frontiers Conference
    May 4 - 6, 2005
    Ischia, Italy

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    Cited By

    View all
    • (2019)Exploring Adaptive Cache for Reconfigurable VLIW ProcessorIEEE Access10.1109/ACCESS.2019.29195897(72634-72646)Online publication date: 2019
    • (2014)A workload independent energy reduction strategy for D-NUCA cachesThe Journal of Supercomputing10.1007/s11227-013-1033-568:1(157-182)Online publication date: 1-Apr-2014
    • (2013)Leakage energy estimates for HPC applicationsProceedings of the 1st International Workshop on Energy Efficient Supercomputing10.1145/2536430.2536431(1-8)Online publication date: 17-Nov-2013
    • (2010)Way adaptable D-NUCA cachesInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2010.0345422:3/4(215-228)Online publication date: 1-Aug-2010
    • (2008)Leveraging Data Promotion for Low Power D-NUCA CachesProceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools10.1109/DSD.2008.52(307-316)Online publication date: 3-Sep-2008
    • (2008)Reducing Leakage through Filter CacheProceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools10.1109/DSD.2008.123(334-341)Online publication date: 3-Sep-2008
    • (2007)Improving power efficiency of D-NUCA cachesACM SIGARCH Computer Architecture News10.1145/1327312.132732135:4(53-58)Online publication date: 1-Sep-2007
    • (2007)Reducing leakage in power-saving capable caches for embedded systems by using a filter cacheProceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture10.1145/1327171.1327183(97-104)Online publication date: 16-Sep-2007
    • (2007)Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM ArraysProceedings of the 8th International Symposium on Quality Electronic Design10.1109/ISQED.2007.97(185-191)Online publication date: 26-Mar-2007

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