Article

Minimizing peak current via opposite-phase clock tree

Authors:

Yow-Tyng Nieh,

Shih-Hsu Huang,

Sheng-Yu HsuAuthors Info & Claims

DAC '05: Proceedings of the 42nd annual Design Automation Conference

Pages 182 - 185

https://doi.org/10.1145/1065579.1065629

Published: 13 June 2005 Publication History

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Abstract

Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of the peak current caused by the clock tree. In this paper, we propose an opposite-phase scheme for peak current reduction. Our basic idea is to divide the clock buffers at each level of the clock tree into two sets: an half of clock buffers operate at the same phase of the clock source, and another half of clock buffers operate at the opposite phase of the clock source. Consequently, our approach can reduce the peak current of the clock tree nearly 50%. Experimental data consistently show that our approach works well in practice.

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Cited By

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Nedalgi DN LSiddamal S(2023)Supply Noise and Peak Current Reduction in High-Speed Output Drivers2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)10.1109/VLSID57277.2023.00038(127-132)Online publication date: Jan-2023
https://doi.org/10.1109/VLSID57277.2023.00038
Beheshti-Shirazi SNazari NGubbi KLatibari BRafatirad SHomayoun HSasan AManoj P(2023)Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop MinimizationIEEE Access10.1109/ACCESS.2023.330453411(87869-87886)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3304534
Beheshti-Shirazi SVakil AManoj SSavidis IHomayoun HSasan AChen YZhirnov VSasan ASavidis I(2021)A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR DropProceedings of the 2021 on Great Lakes Symposium on VLSI10.1145/3453688.3461754(181-187)Online publication date: 22-Jun-2021
https://dl.acm.org/doi/10.1145/3453688.3461754
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Index Terms

Minimizing peak current via opposite-phase clock tree
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

DAC '05: Proceedings of the 42nd annual Design Automation Conference

June 2005

984 pages

ISBN:1595930582

DOI:10.1145/1065579

General Chair:
William H. Joyner
IBM Corp./SRC
,
Program Chairs:
Grant E. Martin
Tensilica, Inc.
,
Andrew B. Kahng
University of California at San Diego, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 13 June 2005

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June 13 - 17, 2005

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Nedalgi DN LSiddamal S(2023)Supply Noise and Peak Current Reduction in High-Speed Output Drivers2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)10.1109/VLSID57277.2023.00038(127-132)Online publication date: Jan-2023
https://doi.org/10.1109/VLSID57277.2023.00038
Beheshti-Shirazi SNazari NGubbi KLatibari BRafatirad SHomayoun HSasan AManoj P(2023)Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop MinimizationIEEE Access10.1109/ACCESS.2023.330453411(87869-87886)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3304534
Beheshti-Shirazi SVakil AManoj SSavidis IHomayoun HSasan AChen YZhirnov VSasan ASavidis I(2021)A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR DropProceedings of the 2021 on Great Lakes Symposium on VLSI10.1145/3453688.3461754(181-187)Online publication date: 22-Jun-2021
https://dl.acm.org/doi/10.1145/3453688.3461754
Van Toan NMinh Tung DLee J(2018)Analysis of Clock Scheduling in Frequency Domain for Digital Switching Noise SuppressionsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.283081026:9(1685-1698)Online publication date: Sep-2018
https://doi.org/10.1109/TVLSI.2018.2830810
Kim JKim T(2018)Clock buffer and flip-flop co-optimization for reducing peak current noise2018 19th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2018.8357271(94-99)Online publication date: Mar-2018
https://doi.org/10.1109/ISQED.2018.8357271
Nath BMajumder A(2017)Binary Counter Based Gated Clock Tree for Integrated CPU Chip2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)10.1109/iNIS.2017.54(229-233)Online publication date: Dec-2017
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Chou CLai YChang YWang CCheng LHuang SChang S(2017)Ping-Pong MeshIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.256520236:1(146-155)Online publication date: 1-Jan-2017
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Bhamidipati LGunna BHomayoun HSasan A(2017)A Power Delivery Network and Cell Placement Aware IR-Drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful Skews2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2017.55(272-277)Online publication date: Jul-2017
https://doi.org/10.1109/ISVLSI.2017.55
Cheng C(2016)Toward a Faster Screening of Faulty Digital Chips via Current-Bound Estimation Based on Device Size and Threshold VoltageJournal of Low Power Electronics and Applications10.3390/jlpea60200066:2(6)Online publication date: 6-May-2016
https://doi.org/10.3390/jlpea6020006
Fan XStegmann MSchrape OZeidler SJensen IThorsen JBjerregaard TKrstic M(2016)Frequency-Domain Optimization of Digital Switching Noise Based on Clock SchedulingIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2016.254611863:7(982-993)Online publication date: Jul-2016
https://doi.org/10.1109/TCSI.2016.2546118
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Recommendations

Type-matching clock tree for zero skew clock gating

Opposite-Phase Clock Tree for Peak Current Reduction

Pulsed-latch-based clock tree migration for dynamic power reduction

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