Article

Sign bit reduction encoding for low power applications

Authors:

M. Saneei,

A. Afzali-Kusha,

Z. NavabiAuthors Info & Claims

DAC '05: Proceedings of the 42nd annual Design Automation Conference

Pages 214 - 217

https://doi.org/10.1145/1065579.1065636

Published: 13 June 2005 Publication History

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Abstract

This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers based on this scheme, the dynamic power consumption of some digital systems such as digital filters based on CMOS logic system can be reduced considerably compared to those based on 2's complement implementation. To verify the efficacy of the SBR, a 16-bit multiplier was implemented by this scheme. The results for voice data show an average of 29% to 35% switching reduction compared to the 2's complement implementation. For 16-bit random data, this scheme decreases the switching of 16-bit multipliers by an average of 21%. Finally, the application of the technique to a 16-bit data bus leads up to 14.5% switching reduction on average.

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Cited By

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Song JChen LLu ZLi BLiu ZXue ZSun GLiu W(2024)Cascaded multiplier-free implementation of adaptive anti-jamming filter based on GNSS receiverFrontiers in Physics10.3389/fphy.2024.140423612Online publication date: 3-Jul-2024
https://doi.org/10.3389/fphy.2024.1404236
Meteer OBekooij M(2021)Low-Power Sign-Magnitude FFT Design for FMCW Radar Signal ProcessingWorkshop on Design and Architectures for Signal and Image Processing (14th edition)10.1145/3441110.3441145(52-59)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3441110.3441145

Index Terms

Sign bit reduction encoding for low power applications
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Arithmetic and datapath circuits

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Published In

DAC '05: Proceedings of the 42nd annual Design Automation Conference

June 2005

984 pages

ISBN:1595930582

DOI:10.1145/1065579

General Chair:
William H. Joyner
IBM Corp./SRC
,
Program Chairs:
Grant E. Martin
Tensilica, Inc.
,
Andrew B. Kahng
University of California at San Diego, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 13 June 2005

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DAC05: The 42nd Annual Design Automation Conference 2005

June 13 - 17, 2005

California, Anaheim, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Song JChen LLu ZLi BLiu ZXue ZSun GLiu W(2024)Cascaded multiplier-free implementation of adaptive anti-jamming filter based on GNSS receiverFrontiers in Physics10.3389/fphy.2024.140423612Online publication date: 3-Jul-2024
https://doi.org/10.3389/fphy.2024.1404236
Meteer OBekooij M(2021)Low-Power Sign-Magnitude FFT Design for FMCW Radar Signal ProcessingWorkshop on Design and Architectures for Signal and Image Processing (14th edition)10.1145/3441110.3441145(52-59)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3441110.3441145

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