skip to main content
10.1145/1065579.1065692acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
Article

Multiplexer restructuring for FPGA implementation cost reduction

Published: 13 June 2005 Publication History

Abstract

This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number of Lookup Tables (LUTs) needed to implement multiplexers. The algorithm relies on reimplementing 2:1 multiplexer trees using efficient 4:1 multiplexers. The key to the algorithm's performance lies in exploiting the observation that most multiplexers occur in busses. New optimizations are employed which pay a small cost in logic that is shared across the bus to achieve a reduction in the logic required for every bit of the bus.

References

[1]
A High Performance 32-bit ALU for Programmable Logic. P. Metzgen. Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field Programmable Gate Arrays. Pp 61--70. 2004.
[2]
FPGA Performance Benchmarking Methodology, White Paper, http://www.altera.com
[3]
The Stratix Device Handbook (Vol 1). Altera Corporation, 2004.
[4]
E. M. Sentovich et al. "SIS: A System for Sequential Circuit Synthesis." Technical Report, University of California at Berkeley, 1992, Memorandum No. UCB/ERL M92/41
[5]
J. Cong and Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table based FPGA Designs", IEEE Trans. CAD Vol 13, No 1, pp. 1--12, 1994.
[6]
V. Manohararajah, S.D. Brown and Z. Vranesic, "Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping" http://sj-wiki/twiki/pub/SJSW/AlteraPublications/tmap.pdf, in Proc. of the Int'l Workshop on Logic Synthesis 2004
[7]
D. Lewis et al, C. Wysocki and R. Cliff, "The Stratix Routing and Logic Architecture" http://sj-wiki/twiki/pub/SJSW/AlteraPublications/stratix.pdf, in Proc. ACM/SIGDA Int'l Symposium on FPGAs (FPGA 2003), pp.12--20, 2003
[8]
David Lewis et al, "The Stratix-II Routing and Logic Architecture" http://sj-wiki/twiki/pub/SJSW/AlteraPublications/f84-lewis.pdf. 2005 Int'l Symposium on FPGAs (FPGA 2005)

Cited By

View all
  • (2023)Optimization of Multiplexer Combination in RTL Logic Synthesis2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218464(121-125)Online publication date: 8-May-2023
  • (2023)Fundamentals of Logic LockingUnderstanding Logic Locking10.1007/978-3-031-37989-5_5(89-107)Online publication date: 26-Jun-2023
  • (2021)Hardware Compilation Using SSASSA-based Compiler Design10.1007/978-3-030-80515-9_23(329-345)Online publication date: 12-Jun-2021
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
DAC '05: Proceedings of the 42nd annual Design Automation Conference
June 2005
984 pages
ISBN:1595930582
DOI:10.1145/1065579
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2005

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. FPGA
  2. busses
  3. logic optimization
  4. multiplexers
  5. recoding
  6. restructuring
  7. synthesis

Qualifiers

  • Article

Conference

DAC05
Sponsor:
DAC05: The 42nd Annual Design Automation Conference 2005
June 13 - 17, 2005
California, Anaheim, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25
62nd ACM/IEEE Design Automation Conference
June 22 - 26, 2025
San Francisco , CA , USA

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)13
  • Downloads (Last 6 weeks)1
Reflects downloads up to 20 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2023)Optimization of Multiplexer Combination in RTL Logic Synthesis2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218464(121-125)Online publication date: 8-May-2023
  • (2023)Fundamentals of Logic LockingUnderstanding Logic Locking10.1007/978-3-031-37989-5_5(89-107)Online publication date: 26-Jun-2023
  • (2021)Hardware Compilation Using SSASSA-based Compiler Design10.1007/978-3-030-80515-9_23(329-345)Online publication date: 12-Jun-2021
  • (2016)An efficient prompt multiplexers using Memristor2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET)10.1109/WiSPNET.2016.7566091(65-69)Online publication date: Mar-2016
  • (2014)Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.228428122:10(2067-2080)Online publication date: Oct-2014
  • (2014)Faster synthesis of combinational logic based on multiplexer trees and binary decision diagrams2014 IEEE 12th IEEE International Conference on Emerging eLearning Technologies and Applications (ICETA)10.1109/ICETA.2014.7107591(239-244)Online publication date: Dec-2014
  • (2013)A Case for Heterogeneous Technology-MappingProceedings of the 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines10.1109/FCCM.2013.19(53-56)Online publication date: 28-Apr-2013
  • (2012)Reducing the cost of floating-point mantissa alignment and normalization in FPGAsProceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays10.1145/2145694.2145738(255-264)Online publication date: 22-Feb-2012
  • (2012)Switch Design for Soft Interconnection NetworksEmbedded Systems Design with FPGAs10.1007/978-1-4614-1362-2_6(125-147)Online publication date: 1-Nov-2012
  • (2011)Comparing FPGA vs. custom cmos and the impact on processor microarchitectureProceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1950413.1950419(5-14)Online publication date: 27-Feb-2011
  • Show More Cited By

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media