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OPERA: optimization with ellipsoidal uncertainty for robust analog IC design

Published: 13 June 2005 Publication History

Abstract

As the design-manufacturing interface becomes increasingly complicated with IC technology scaling, the corresponding process variability poses great challenges for nanoscale analog/RF design. Design optimization based on the enumeration of process corners has been widely used, but can suffer from inefficiency and overdesign. In this paper we propose to formulate the analog and RF design with variability problem as a special type of robust optimization problem, namely robust geometric programming. The statistical variations in both the process parameters and design variables are captured by a pre-specified confidence ellipsoid. Using such optimization with ellipsoidal uncertainy approach, robust design can be obtained with guaranteed yield bound and lower design cost, and most importantly, the problem size grows linearly with number of uncertain parameters. Numerical examples demonstrate the efficiency and reveal the trade-off between the design cost versus the yield requirement. We will also demonstrate significant improvement in the design cost using this approach compared with corner-enumeration optimization.

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  • (2022)Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC52403.2022.9712559(80-85)Online publication date: 17-Jan-2022
  • (2020)Chance-Constrained and Yield-Aware Optimization of Photonic ICs with Non-Gaussian Correlated Process VariationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.2968582(1-1)Online publication date: 2020
  • (2017)Tensor ComputationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261887936:4(521-536)Online publication date: 1-Apr-2017
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    cover image ACM Conferences
    DAC '05: Proceedings of the 42nd annual Design Automation Conference
    June 2005
    984 pages
    ISBN:1595930582
    DOI:10.1145/1065579
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 13 June 2005

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    Author Tags

    1. optimization
    2. statistical

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    June 13 - 17, 2005
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    View all
    • (2022)Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC52403.2022.9712559(80-85)Online publication date: 17-Jan-2022
    • (2020)Chance-Constrained and Yield-Aware Optimization of Photonic ICs with Non-Gaussian Correlated Process VariationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.2968582(1-1)Online publication date: 2020
    • (2017)Tensor ComputationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261887936:4(521-536)Online publication date: 1-Apr-2017
    • (2017)Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detectionIET Circuits, Devices & Systems10.1049/iet-cds.2015.032511:1(1-9)Online publication date: 1-Jan-2017
    • (2015)Overview of nano-electronics printing techniques and patterning defects detection2015 IEEE UP Section Conference on Electrical Computer and Electronics (UPCON)10.1109/UPCON.2015.7456724(1-6)Online publication date: Dec-2015
    • (2015)Multi-dimensional design layout analysis in ASIC manufacturing2015 IEEE Students Conference on Engineering and Systems (SCES)10.1109/SCES.2015.7506449(1-5)Online publication date: Nov-2015
    • (2015)Multiple-patterning and systematic wafer inspection of VLSI devices for yield2015 Annual IEEE India Conference (INDICON)10.1109/INDICON.2015.7443755(1-6)Online publication date: Dec-2015
    • (2014)Robust Optimization for Gate Sizing Considering Non-Gaussian Local VariationsApplied Mathematics10.4236/am.2014.51624505:16(2558-2569)Online publication date: 2014
    • (2014)Polynomial metamodel based fast optimization of nano-CMOS oscillator circuitsAnalog Integrated Circuits and Signal Processing10.1007/s10470-014-0284-279:3(437-453)Online publication date: 1-Jun-2014
    • (2013)Modeling and design of CMOS analog circuits through hierarchical abstractionIntegration, the VLSI Journal10.1016/j.vlsi.2013.02.00146:4(449-462)Online publication date: 1-Sep-2013
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