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Streamline verification process with formal property verification to meet highly compressed design cycle

Published: 13 June 2005 Publication History

Abstract

In this paper, I describe a methodology and tool flow for using formal verification effectively to reduce the verification burden in large custom ASIC designs.

References

[1]
Malachowsky, C., "When 10M Gates Just Isn't Enough: The GPU Challenge", DAC, 2002.
[2]
Smith, D., "NVIDIA: Scaling metholodogy", Proceedings of EDP, 2002.
[3]
Magellan product description web site, http://www.synopsys.com/products/magellan/magellan.html, 2005.
[5]
Ip, N., and Foster, H., "Design Illumination". DesignCon 2005.
[6]
Jasper Design Automation, "JasperGold 3.1 Reference

Cited By

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  • (2008)Challenges in using system-level models for RTL verificationProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391676(812-815)Online publication date: 8-Jun-2008
  • (2008)Assertion-based verification of a 32 thread SPARC™ CMT microprocessorProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391535(256-261)Online publication date: 8-Jun-2008

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  1. Streamline verification process with formal property verification to meet highly compressed design cycle

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      cover image ACM Conferences
      DAC '05: Proceedings of the 42nd annual Design Automation Conference
      June 2005
      984 pages
      ISBN:1595930582
      DOI:10.1145/1065579
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      New York, NY, United States

      Publication History

      Published: 13 June 2005

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      1. formal verification

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      DAC05: The 42nd Annual Design Automation Conference 2005
      June 13 - 17, 2005
      California, Anaheim, USA

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      Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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      Cited By

      View all
      • (2008)Challenges in using system-level models for RTL verificationProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391676(812-815)Online publication date: 8-Jun-2008
      • (2008)Assertion-based verification of a 32 thread SPARC™ CMT microprocessorProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391535(256-261)Online publication date: 8-Jun-2008

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