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BEOL variability and impact on RC extraction

Published: 13 June 2005 Publication History

Abstract

Historically, Back End of Line (BEOL) or interconnect resistance and capacitance have been viewed as parasitic components. They have now become key parameters with significant impact on circuit performance and signal integrity. This paper examines the types of BEOL variations and their impact on RC extraction. The importance of modeling systematic effects in RC extraction is discussed. The need for minimizing the computational error in RC extraction before incorporating random process variations is emphasized.

Reference

[1]
Nagaraj NS et. al., "Benchmarks for Interconnect Parasitic Resistance and Capacitance" in proc. of ISQED 2003.

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  • (2014)An Efficient Methodology for Estimating Interconnect Crosstalk Noise in Deep-Submicron TechnologiesAdvanced Materials Research10.4028/www.scientific.net/AMR.989-994.2647989-994(2647-2650)Online publication date: Jul-2014
  • (2013)Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explainedIEEE Design & Test10.1109/MDT.2009.130(1-1)Online publication date: 2013
  • (2011)Characterization and analysis of pattern dependent variation-aware interconnects for a 65nm technology2011 9th IEEE International Conference on ASIC10.1109/ASICON.2011.6157339(854-857)Online publication date: Oct-2011
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cover image ACM Conferences
DAC '05: Proceedings of the 42nd annual Design Automation Conference
June 2005
984 pages
ISBN:1595930582
DOI:10.1145/1065579
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2005

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Author Tags

  1. extraction
  2. interconnect
  3. process variation

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DAC05
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DAC05: The 42nd Annual Design Automation Conference 2005
June 13 - 17, 2005
California, Anaheim, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all
  • (2014)An Efficient Methodology for Estimating Interconnect Crosstalk Noise in Deep-Submicron TechnologiesAdvanced Materials Research10.4028/www.scientific.net/AMR.989-994.2647989-994(2647-2650)Online publication date: Jul-2014
  • (2013)Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explainedIEEE Design & Test10.1109/MDT.2009.130(1-1)Online publication date: 2013
  • (2011)Characterization and analysis of pattern dependent variation-aware interconnects for a 65nm technology2011 9th IEEE International Conference on ASIC10.1109/ASICON.2011.6157339(854-857)Online publication date: Oct-2011
  • (2010)Data learning based diagnosisProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899775(247-254)Online publication date: 18-Jan-2010
  • (2010)Data learning based diagnosis2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2010.5419888(247-254)Online publication date: Jan-2010
  • (2009)FastYieldProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509650(61-66)Online publication date: 19-Jan-2009
  • (2008)Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained2008 IEEE International Test Conference10.1109/TEST.2008.4700588(1-10)Online publication date: Oct-2008
  • (2007)Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability2007 IEEE International SOC Conference10.1109/SOCC.2007.4545471(261-268)Online publication date: Sep-2007
  • (2006)Crosstalk analysis in nanometer technologiesProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127967(253-258)Online publication date: 30-Apr-2006
  • (2006)Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologiesProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127914(14-18)Online publication date: 30-Apr-2006
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