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MiniBit: bit-width optimization via affine arithmetic

Published: 13 June 2005 Publication History

Abstract

MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static analysis via affine arithmetic. We describe methods to minimize both the integer and fraction parts of fixed-point signals with the aim of minimizing circuit area. Our range analysis technique identifies the number of integer bits required. For precision analysis, we employ a semi-analytical approach with analytical error models in conjunction with adaptive simulated annealing to find the optimum number of fraction bits. Improvements for a given design reduce area and latency by up to 20% and 12% respectively, over optimum uniform fraction bit-widths on a Xilinx Virtex-4 FPGA.

References

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A. Abdul Gaffar, O. Mencer, W. Luk, and P. Cheung. Unifying bit-width optimisation for fixed-point and floating-point designs. In Proc. IEEE Symp. Field-Programmable Custom Computing Machines, pages 79--88, 2004.
[2]
R. Cmar, L. Rijnders, P. Schaumont, S. Vernalde, and I. Bolsens. A methodology and design environment for DSP ASIC fixed point refinement. In Proc. ACM/IEEE Design Automation and Test in Europe Conf., pages 271--276, 1999.
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C. Fang, R. Rutenbar, and T. Chen. Fast, accurate static analysis for fixed-point finite-precision effects in DSP designs. In Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design, pages 275--282, 2003.
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C. Fang, R. Rutenbar, M. Püschel, and T. Chen. Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling. In Proc. ACM/IEEE Design Automation Conf., pages 496--501, 2003.
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L. Ingber. Adaptive Simulated Annealing (ASA) 25.15, 2004. http://www.ingber.com/#ASA.
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L. de Figueiredo and J. Stolfi. Self-validated numerical methods and applications. In Brazilian Mathematics Colloquium monograph. IMPA, Brazil, 1997.
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D. Menard and O. Sentieys. Automatic evaluation of the accuracy of fixed-point algorithms. In Proc. ACM/IEEE Design Automation and Test in Europe Conf., pages 1530--1591, 2002.
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O. Mencer, D. Pearce, L. Howes, and W. Luk. Design space exploration with A Stream Compiler. In Proc. IEEE Int'l Conf. Field-Programmable Technology, pages 270--277, 2003.

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Published In

cover image ACM Conferences
DAC '05: Proceedings of the 42nd annual Design Automation Conference
June 2005
984 pages
ISBN:1595930582
DOI:10.1145/1065579
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2005

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Author Tags

  1. FPGA
  2. affine arithmetic
  3. annealing
  4. bit-width
  5. fixed-point
  6. simulated

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DAC05
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DAC05: The 42nd Annual Design Automation Conference 2005
June 13 - 17, 2005
California, Anaheim, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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  • (2024)CoSense: Compiler Optimizations using Sensor Technical SpecificationsProceedings of the 33rd ACM SIGPLAN International Conference on Compiler Construction10.1145/3640537.3641576(73-85)Online publication date: 17-Feb-2024
  • (2024)Wordlength Optimization for Custom Floating-Point SystemsDesign and Architectures for Signal and Image Processing10.1007/978-3-031-62874-0_4(43-55)Online publication date: 17-Jan-2024
  • (2023)Automatic Word Length Selection with Boundary Conditions for HIL of Power ConvertersElectronics10.3390/electronics1216348812:16(3488)Online publication date: 17-Aug-2023
  • (2020)HeteroRefactorProceedings of the ACM/IEEE 42nd International Conference on Software Engineering10.1145/3377811.3380340(493-505)Online publication date: 27-Jun-2020
  • (2020)Acceleration of Simulation Models Through Automatic Conversion to FPGA Hardware2020 30th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL50879.2020.00068(359-360)Online publication date: Aug-2020
  • (2019)Optimization and Hardware Implementation of Image and Video Watermarking for Low-Cost ApplicationsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2019.290719166:6(2088-2101)Online publication date: Jun-2019
  • (2018)ACEDProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3195981(1-6)Online publication date: 24-Jun-2018
  • (2018)Threshold-Guided Design and Optimization for Harris Corner Detector ArchitectureIEEE Transactions on Circuits and Systems for Video Technology10.1109/TCSVT.2017.275799828:12(3516-3526)Online publication date: Dec-2018
  • (2018)Analysis of Finite Word-Length Effects in Fixed-Point SystemsHandbook of Signal Processing Systems10.1007/978-3-319-91734-4_29(1063-1101)Online publication date: 14-Oct-2018
  • (2017)Efficient floating point precision tuning for approximate computing2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2017.7858297(63-68)Online publication date: Jan-2017
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