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Performance space modeling for hierarchical synthesis of analog integrated circuits

Published: 13 June 2005 Publication History

Abstract

Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient methods that can handle design hierarchy, in terms of both performance estimation and hierarchical design optimization method. This paper discusses and compares recent developments in this area, with special emphasis on automated modeling and on multi-objective bottom-up hierarchical design.

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  • (2024)MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.341689443:12(4740-4752)Online publication date: Dec-2024
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  • (2019)Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP RelaxationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.284859038:8(1385-1398)Online publication date: Aug-2019
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cover image ACM Conferences
DAC '05: Proceedings of the 42nd annual Design Automation Conference
June 2005
984 pages
ISBN:1595930582
DOI:10.1145/1065579
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 13 June 2005

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  1. hierarchical synthesis

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DAC05: The 42nd Annual Design Automation Conference 2005
June 13 - 17, 2005
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Cited By

View all
  • (2024)MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.341689443:12(4740-4752)Online publication date: Dec-2024
  • (2022)Bayesian Deep Active Learning for Analog Circuit Performance Classification2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937416(3018-3022)Online publication date: 28-May-2022
  • (2019)Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP RelaxationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.284859038:8(1385-1398)Online publication date: Aug-2019
  • (2016)Previous Works on Automatic Analog IC SizingAutomatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects10.1007/978-3-319-42037-0_2(13-37)Online publication date: 30-Jul-2016
  • (2015)Automatic design for analog/RF front-end system in 802.11ac receiverThe 20th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2015.7059048(454-459)Online publication date: Jan-2015
  • (2014)Yield-Aware Pareto Front Extraction for Discrete Hierarchical Optimization of Analog CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.233156333:10(1437-1449)Online publication date: Oct-2014
  • (2013)Modeling and design of CMOS analog circuits through hierarchical abstractionIntegration, the VLSI Journal10.1016/j.vlsi.2013.02.00146:4(449-462)Online publication date: 1-Sep-2013
  • (2013)Basic Concepts and BackgroundAutomated Design of Analog and High-frequency Circuits10.1007/978-3-642-39162-0_1(1-17)Online publication date: 17-Aug-2013
  • (2009)A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC RefinementIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E92.A.3193E92-A:12(3193-3202)Online publication date: 2009
  • (2009)Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits2009 22nd International Conference on VLSI Design10.1109/VLSI.Design.2009.67(131-136)Online publication date: Jan-2009
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