Article

Exploring technology alternatives for nano-scale FPGA interconnects

Authors:

N. Vijaykrishnan,

M. J. IrwinAuthors Info & Claims

DAC '05: Proceedings of the 42nd annual Design Automation Conference

Pages 921 - 926

https://doi.org/10.1145/1065579.1065820

Published: 13 June 2005 Publication History

Abstract

Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular. With their regular structures, they are particularly amenable to scaling to smaller technologies. On the other hand, there have been significant advances in nano-electronics fabrication over the past few years. In this paper we explore FPGA devices of the next decade using nano-wires and molecular switches for programmable interconnect, and compare them to traditional SRAM-based FPGAs that use pass transistors as switches (scaled to 22nm). We show that by using nano-wires and molecular switches, it is possible to reduce the area of the FPGA by 70% and improve performance.

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Cited By

NAMBA KTAKASHINA NITO H(2013)Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGAIEICE Transactions on Information and Systems10.1587/transinf.E96.D.1613E96.D:8(1613-1623)Online publication date: 2013
https://doi.org/10.1587/transinf.E96.D.1613
Ho Yoon JJung HHwan Lee MHwan Kim GJi Song SYeong Seok JJean Yoon KSeong Hwang CBesland MTranchant JSouchier EMoreau PSalmon SCorraze BJanod ECario LZazpe RUngureanu MLlopis RGolmar FStoliar PCasanova FEduardo Hueso LHermes CWimmer MMenzel SFleck KRana VSalinga MBöttger UBruchhaus RWuttig MWaser RLentz FHermes CRösgen BSelle TBruchhaus RRana VWaser RMarchewka AMenzel SBöttger UWaser RHoskins BAlibart FStrukov DPellegrino LManca NKanki TTanaka HBiasotti MBellingeri ESergio Siri AMarré DM. Padilha AMartini Dalpian GReily Rocha AProdromakis TSalaoru IKhiat AToumazou CGale EMadhavan AAdam GAlibart FGao LStrukov DWamwangi DWelnic WWuttig MGholipour BHuang CAnastasopoulos AAl‐Saab FHayden BHewak DLan REndo RKuwahara MKobayashi YSusa MBaumeister PWortmann DBlügel SMazzarello RLi YZhang WRonneberger ISimon RGallus JBessas DSergueev IWille HPierre Hermann RLuckas JRausch PKrebs DZalden PBoltz JRaty JSalinga MLongeaud CWuttig MKim HKim DPhark SHong SPark CHerpers ABruchhaus RVerbeeck JEgoavil RBorgatti FPanaccione GOffi FDittmann RClima SSankaran KMees MYin Chen YGoux LGovoreanu BWouters DKittl JJurczak MPourtois GCalka PMartinez EDelaye VLafond DAudoit GMariolle DChevalier NGrampeix HCagli CJousseaume VGuedj CShrestha POchia ACheung KCampbell JBaumgart HHarris GScherff MMeyer BScholz JHoffmann JJooss CXiao BTada TGu TTawara AWatanabe SYoung TYang YChang THsu KChen CBurkert AValov IStaikov GWaser Rvan den Hurk JValov IWaser RValov ITappertzhofen Svan der Hurk JWaser RAdam GAlibart FGao LHoskins BStrukov DJean Yoon KJi Song SKim GSeok JHo Yoon JSeong Hwang CYoon JYoon KShuai YWu CZhang WZhou SBürger DSlesazeck SMikolajick THelm MSchmidt HGale EPearson DKitson SAdamatzky ACostello BLehtonen EPoikonen JLaiho MKanerva PLim HJang HJeong DCao XJiang MZhang FLiu XJin PZhang KTangirala MShrestha PBaumgart HKittiwatanakul SLu JWolf SPallem VDussarrat CPinto SKrishna RDias CPimentel GOliveira GTeixeira JAguiar PTitus EGracio JVentura JAraujo J(2013)Poster: Memristive SystemsFrontiers in Electronic Materials10.1002/9783527667703.ch67(523-587)Online publication date: 30-Apr-2013
https://doi.org/10.1002/9783527667703.ch67
Madhavan AStrukov D(2012)Mapping of image and network processing tasks on high-throughput CMOL FPGA circuits2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)10.1109/VLSI-SoC.2012.7332081(82-87)Online publication date: Oct-2012
https://doi.org/10.1109/VLSI-SoC.2012.7332081
Show More Cited By

Index Terms

Exploring technology alternatives for nano-scale FPGA interconnects
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

cover image ACM Conferences

DAC '05: Proceedings of the 42nd annual Design Automation Conference

June 2005

984 pages

ISBN:1595930582

DOI:10.1145/1065579

General Chair:
William H. Joyner
IBM Corp./SRC
,
Program Chairs:
Grant E. Martin
Tensilica, Inc.
,
Andrew B. Kahng
University of California at San Diego, CA

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 13 June 2005

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June 13 - 17, 2005

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Cited By

NAMBA KTAKASHINA NITO H(2013)Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGAIEICE Transactions on Information and Systems10.1587/transinf.E96.D.1613E96.D:8(1613-1623)Online publication date: 2013
https://doi.org/10.1587/transinf.E96.D.1613
Ho Yoon JJung HHwan Lee MHwan Kim GJi Song SYeong Seok JJean Yoon KSeong Hwang CBesland MTranchant JSouchier EMoreau PSalmon SCorraze BJanod ECario LZazpe RUngureanu MLlopis RGolmar FStoliar PCasanova FEduardo Hueso LHermes CWimmer MMenzel SFleck KRana VSalinga MBöttger UBruchhaus RWuttig MWaser RLentz FHermes CRösgen BSelle TBruchhaus RRana VWaser RMarchewka AMenzel SBöttger UWaser RHoskins BAlibart FStrukov DPellegrino LManca NKanki TTanaka HBiasotti MBellingeri ESergio Siri AMarré DM. Padilha AMartini Dalpian GReily Rocha AProdromakis TSalaoru IKhiat AToumazou CGale EMadhavan AAdam GAlibart FGao LStrukov DWamwangi DWelnic WWuttig MGholipour BHuang CAnastasopoulos AAl‐Saab FHayden BHewak DLan REndo RKuwahara MKobayashi YSusa MBaumeister PWortmann DBlügel SMazzarello RLi YZhang WRonneberger ISimon RGallus JBessas DSergueev IWille HPierre Hermann RLuckas JRausch PKrebs DZalden PBoltz JRaty JSalinga MLongeaud CWuttig MKim HKim DPhark SHong SPark CHerpers ABruchhaus RVerbeeck JEgoavil RBorgatti FPanaccione GOffi FDittmann RClima SSankaran KMees MYin Chen YGoux LGovoreanu BWouters DKittl JJurczak MPourtois GCalka PMartinez EDelaye VLafond DAudoit GMariolle DChevalier NGrampeix HCagli CJousseaume VGuedj CShrestha POchia ACheung KCampbell JBaumgart HHarris GScherff MMeyer BScholz JHoffmann JJooss CXiao BTada TGu TTawara AWatanabe SYoung TYang YChang THsu KChen CBurkert AValov IStaikov GWaser Rvan den Hurk JValov IWaser RValov ITappertzhofen Svan der Hurk JWaser RAdam GAlibart FGao LHoskins BStrukov DJean Yoon KJi Song SKim GSeok JHo Yoon JSeong Hwang CYoon JYoon KShuai YWu CZhang WZhou SBürger DSlesazeck SMikolajick THelm MSchmidt HGale EPearson DKitson SAdamatzky ACostello BLehtonen EPoikonen JLaiho MKanerva PLim HJang HJeong DCao XJiang MZhang FLiu XJin PZhang KTangirala MShrestha PBaumgart HKittiwatanakul SLu JWolf SPallem VDussarrat CPinto SKrishna RDias CPimentel GOliveira GTeixeira JAguiar PTitus EGracio JVentura JAraujo J(2013)Poster: Memristive SystemsFrontiers in Electronic Materials10.1002/9783527667703.ch67(523-587)Online publication date: 30-Apr-2013
https://doi.org/10.1002/9783527667703.ch67
Madhavan AStrukov D(2012)Mapping of image and network processing tasks on high-throughput CMOL FPGA circuits2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)10.1109/VLSI-SoC.2012.7332081(82-87)Online publication date: Oct-2012
https://doi.org/10.1109/VLSI-SoC.2012.7332081
Madhavan AStrukov D(2012)Mapping of image and network processing tasks on high-throughput CMOL FPGA circuits2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)10.1109/VLSI-SoC.2012.6379010(82-87)Online publication date: Oct-2012
https://doi.org/10.1109/VLSI-SoC.2012.6379010
Paul SBhunia S(2012)A Scalable Memory-Based Reconfigurable Computing Framework for Nanoscale CrossbarIEEE Transactions on Nanotechnology10.1109/TNANO.2010.204155611:3(451-462)Online publication date: 1-May-2012
https://dl.acm.org/doi/10.1109/TNANO.2010.2041556
Gaillardon PClermidy FO’Connor ILiu JAmadou MNicolescu G(2011)Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping MethodACM Journal on Emerging Technologies in Computing Systems10.1145/1899390.18993937:1(1-23)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1145/1899390.1899393
Kim KShin SKang S(2011)Field Programmable Stateful Logic ArrayIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.216506730:12(1800-1813)Online publication date: 1-Dec-2011
https://dl.acm.org/doi/10.1109/TCAD.2011.2165067
Strukov DMishchenko ADe Micheli GAl-Hashimi BMueller WMacii E(2010)Monolithically stackable hybrid FPGAProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871087(661-666)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871087
Haselman MHauck S(2010)The Future of Integrated Circuits: A Survey of NanoelectronicsProceedings of the IEEE10.1109/JPROC.2009.203235698:1(11-38)Online publication date: Jan-2010
https://doi.org/10.1109/JPROC.2009.2032356
Singh Duksh YKaushik BSarkar SSingh R(2010)Performance comparison of carbon nanotube, nickel silicide nanowire and copper VLSI interconnectsJournal of Engineering, Design and Technology10.1108/172605310110861998:3(334-353)Online publication date: 12-Oct-2010
https://doi.org/10.1108/17260531011086199
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