skip to main content
10.1145/1065910.1065934acmconferencesArticle/Chapter ViewAbstractPublication PagescpsweekConference Proceedingsconference-collections
Article

A sample-based cache mapping scheme

Published: 15 June 2005 Publication History

Abstract

Applications running on the StrongARM SA-1110 or XScale processor cores can specify cache mapping for each virtual page to achieve better cache utilization. In this work, we describe a method to efficiently perform cache mapping. Under this scheme, we select a number of loops for sampling. These loops are selected automatically based on clock profiling information. We formulate the optimal cache mapping problem as an Integer Linear Programming (ILP) problem. Experiments performed on 14 test programs show speedups in 13 of them (over the default mapping) after applying our sample-based cache mapping scheme. The geometric mean of program speedups for all the 14 test programs is 1.098. Furthermore, compared with a previous heuristic method which uses the full memory trace, the sample-based method performs cache mapping faster by an order of magnitude without sacrificing the quality of mapping.

References

[1]
Matthew Arnold and Barbara G. Ryder. A framework for reducing the cost of instrumented code. In SIGPLAN Conference on Programming Language Design and Implementation, pages 168--179, 2001.
[2]
Kennith K. Chan, Cyrus C. Hay, John R. Keller, Gordon P. Kurpanek, Francis X. Schumacher, and Jason Zheng. Design of HP PA 7200 CPU. In Hewlett-Packard Journal, February 1996.
[3]
C-H. Chi and H. Deitz. Improving cache performance by selective cache bypass. In the 22nd Hawaii International Conference on System Science, pages 277--285, January 1989.
[4]
D. Chiou, P. Jain, S. Devadas, and L. Rudolph. Dynamic cache partitioning via columnization. In Proceedings of Design Automation Conference, Los Angeles, June 2000.
[5]
Antonio Gonzalez, Carlos Aliagas, and Mateo Valero. A data cache with multiple caching strategies tuned to different types of locality. In Proceedings of International Conference on Supercomputing, pages 338--347, July 1995.
[6]
M. Hirzel and T. Chilimbi. Bursty tracing: A framework for low-overhead temporal profiling, 2001.
[7]
ILOG Inc. ILOG CPLEX 7.1 Reference Manual. 2001.
[8]
Intel Corporation. Intel StrongARM SA-1110 microprocessor developer's manual. http://www.intel.com/design/strong/manuals/278240.htm, October 2001.
[9]
Intel Corporation. Intel PXA250 and PXA210 application processor developer's manual. http://www.intel.com/design/pca/applicationspro cessors/manuals/278693.htm, February 2002.
[10]
Teresa L. Johnson, Daniel A. Connors, Matthew C. Merten, and Wen W. Hwu. Run-time cache bypassing. IEEE Transactions on Computers, 48(12):1338--1354, 1999.
[11]
Teresa L. Johnson and Wenmei W. Hwu. Run-time adaptive cache hierarchy management via reference analysis. In Proceedings of the 24th International Symposium on Computer Architecture, pages 315--326, 1997.
[12]
Richard E. Kessler, Mark D. Hill, and David A. Wood. A comparison of trace-sampling techniques for multi-megabyte caches. IEEE Transactions on Computers, 43(6):664--675, 1994.
[13]
Zhiyuan Li and Rong Xu. Page mapping for heterogeneously partitioned caches: Complexity and heuristics. Journal of Embedded Computing, accepted.
[14]
R. L. Mattson, J. Gecsei, D. R. Slutz, and I. L. Traiger. Evaluation techniques for storage hierarchies. IBM System Journal, 9:78--117, 1970.
[15]
V. Milutinovic, M. Tomasevic, B. Markovic, and M. Tremblay. A new cache architecture concept: the split temporal/spatial cache. In Proceedings of 8th Mediterranean Electrotechnical Conference, pages 1108--1111, May 1996.
[16]
Jude A. Rivers and Edward S. Davidson. Reducing conflicts in direct-mapped caches with a temporality-based design. In Proceedings of the 1996 International Conference on Parallel Processing, volume 1, pages 154--163, 1996.
[17]
Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, and Matt Farrens. Utilizing reuse information in data cache management. In Conference proceedings of the 1998 international conference on Supercomputing, pages 449--456. ACM Press, 1998.
[18]
Shai Rubin, Rastislav Bodik, and Trishul Chilimbi. An efficient profile-analysis framework for data-layout optimizations. In Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages, pages 140--153. ACM Press, 2002.
[19]
Yonghong Song, Rong Xu, Cheng Wang, and Zhiyuan Li. Improving data locality by array contraction. IEEE Trans. Computers, 53(9):1073--1084, 2004.
[20]
Gary Tyson, Matthew Farrens, John Matthews, and Andrew R. Pleszkun. A modified approach to data cache management. In Proceedings of the 28th Annual ACM/IEEE International Symposium on Microarchitecture, pages 93--103, 1995.
[21]
Michael Joseph Wolfe, Carter Shanklin, and Leda Ortega. High Performance Compilers for Parallel Computing. Addison-Wesley Longman Publishing Co., Inc., 1995.
[22]
Rong Xu and Zhiyuan Li. Using cache mapping to improve memory performance of handheld devices. In Proceedings of the 4th IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2004), pages 115--122, Austin, Texas, 2004.

Cited By

View all
  • (2009)Soft-OLPProceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2009.35(246-257)Online publication date: 12-Sep-2009
  • (2007)Fast, accurate design space exploration of embedded systems memory configurationsProceedings of the 2007 ACM symposium on Applied computing10.1145/1244002.1244159(699-706)Online publication date: 11-Mar-2007

Index Terms

  1. A sample-based cache mapping scheme

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    LCTES '05: Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
    June 2005
    248 pages
    ISBN:1595930183
    DOI:10.1145/1065910
    • General Chair:
    • Yunheung Paek,
    • Program Chair:
    • Rajiv Gupta
    • cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 40, Issue 7
      Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
      July 2005
      238 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/1070891
      Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 15 June 2005

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. cache bypass
    2. cache mapping
    3. handheld devices
    4. mini cache
    5. profiling
    6. trace sampling

    Qualifiers

    • Article

    Conference

    LCTES05

    Acceptance Rates

    Overall Acceptance Rate 116 of 438 submissions, 26%

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)1
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 20 Jan 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2009)Soft-OLPProceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2009.35(246-257)Online publication date: 12-Sep-2009
    • (2007)Fast, accurate design space exploration of embedded systems memory configurationsProceedings of the 2007 ACM symposium on Applied computing10.1145/1244002.1244159(699-706)Online publication date: 11-Mar-2007

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media