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The need for a full-chip and package thermal model for thermally optimized IC designs

Published: 08 August 2005 Publication History

Abstract

Modeling and analyzing detailed die temperature with a full-chip thermal model at early design stages is important to discover and avoid potential thermal hazards. However, omitting important aspects of package details in a thermal model can result in significant temperature estimation errors. In this paper, we discuss the applications of an existing compact thermal model that models both die and package temperature details. As an example, a thermally self-consistent leakage power calculation of a POWER4-like microprocessor design is presented. We then demonstrate the importance of including detailed package information in the thermal model by several examples considering the impact of thermal interface material (TIM), which glues the die to the heat spreader. The fact that detailed package information is needed to build an accurate compact thermal model implies a design flow, in which the chip- and package-level compact thermal model acts as a convenient medium for more productive collaborations among circuit designers, computer architects and package designers, leading to early and efficient evaluations of different design tradeoffs for an optimal design from a thermal point of view

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cover image ACM Conferences
ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design
August 2005
400 pages
ISBN:1595931376
DOI:10.1145/1077603
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 August 2005

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Author Tags

  1. leakage
  2. package
  3. temperature-aware design
  4. thermal model

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Cited By

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  • (2023)Efficient transient thermal analysis of chiplet heterogeneous integrationApplied Thermal Engineering10.1016/j.applthermaleng.2023.120609229(120609)Online publication date: Jul-2023
  • (2021)Thermal Aware Device Design Using Hotspot AnalysisAdvances in Automation, Signal Processing, Instrumentation, and Control10.1007/978-981-15-8221-9_245(2627-2637)Online publication date: 5-Mar-2021
  • (2020)A Fast Leakage-Aware Green’s-Function-Based Thermal Simulator for 3-D ChipsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.302346428:11(2342-2355)Online publication date: Nov-2020
  • (2020)ANtarctica: ANalog Thermal Aware, with Reduced Constraint, Technique for Checking & Analysis2020 IEEE International Integrated Reliability Workshop (IIRW)10.1109/IIRW49815.2020.9312856(1-4)Online publication date: Oct-2020
  • (2019)Experimental Characterization of Variation in Power Consumption for Processors of Different Generations2019 International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, Physical and Social Computing (CPSCom) and IEEE Smart Data (SmartData)10.1109/iThings/GreenCom/CPSCom/SmartData.2019.00133(702-710)Online publication date: Jul-2019
  • (2016)Temperature Effect on Dielectric Breakdown and Charges Retention of Nanocrystalline Cadmium Selenide Embedded Zr-Doped HfO2 High- ${k}$ Dielectric Thin FilmIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2016.261768216:4(561-569)Online publication date: Dec-2016
  • (2014)Compact thermal modeling for packaged microprocessor design with practical power mapsIntegration, the VLSI Journal10.1016/j.vlsi.2013.07.00347:1(71-85)Online publication date: 1-Jan-2014
  • (2012)Multidisciplinary Heat Generating Cell Placement Optimization Using Genetic Algorithm and Artificial Neural Networks9th AIAA/ASME Joint Thermophysics and Heat Transfer Conference10.2514/6.2006-3415Online publication date: 15-Jun-2012
  • (2011)Thermal Modeling Technique for Multiple Transistors Within Silicon ChipJournal of Electronic Packaging10.1115/1.4005291133:4(041015)Online publication date: 2011
  • (2011)Variation-Tolerant Adaptive Voltage SystemsManaging Temperature Effects in Nanoscale Adaptive Systems10.1007/978-1-4614-0748-5_4(63-92)Online publication date: 28-Jul-2011
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