Article

Energy reduction in multiprocessor systems using transactional memory

Authors:

Maurice HerlihyAuthors Info & Claims

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

Pages 331 - 334

https://doi.org/10.1145/1077603.1077683

Published: 08 August 2005 Publication History

Abstract

The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Until recently, this trend was mostly true for uniprocessors. In this work we focus on new energy consumption issues unique to multiprocessor systems: synchronization of accesses to shared memory. We investigate and compare different means of providing atomic access to shared memory, including locks and lock-free synchronization (i.e., transactional memory), with respect to energy as well as performance. We show that transactional memory has an advantage in terms of energy consumption over locks, but that this advantage largely depends on the system architecture, the contention level, and the policy of conflict resolution

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Cited By

Issa SRomano PBrorsson M(2015)Green-CMProceedings of the 2015 44th International Conference on Parallel Processing (ICPP)10.1109/ICPP.2015.64(550-559)Online publication date: 1-Sep-2015
https://dl.acm.org/doi/10.1109/ICPP.2015.64
Bonnichsen LPodobas A(2015)Using Transactional Memory to Avoid Blocking in OpenMP Synchronization DirectivesOpenMP: Heterogenous Execution and Data Movements10.1007/978-3-319-24595-9_11(149-161)Online publication date: 26-Nov-2015
https://doi.org/10.1007/978-3-319-24595-9_11
Kim SLee SJun MLee BRo WChung EGaudiot J(2014)$C\!\!-\!\!Lock$IEEE Transactions on Computers10.1109/TC.2013.8463:8(1962-1974)Online publication date: 1-Aug-2014
https://dl.acm.org/doi/10.1109/TC.2013.84
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Index Terms

Energy reduction in multiprocessor systems using transactional memory
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data

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cover image ACM Conferences

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

August 2005

400 pages

ISBN:1595931376

DOI:10.1145/1077603

General Chairs:
Kaushik Roy
Purdue University
,
Vivek Tiwari
Intel

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 August 2005

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ISLPED05: International Symposium on Low Power Electronics and Design

August 8 - 10, 2005

CA, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Issa SRomano PBrorsson M(2015)Green-CMProceedings of the 2015 44th International Conference on Parallel Processing (ICPP)10.1109/ICPP.2015.64(550-559)Online publication date: 1-Sep-2015
https://dl.acm.org/doi/10.1109/ICPP.2015.64
Bonnichsen LPodobas A(2015)Using Transactional Memory to Avoid Blocking in OpenMP Synchronization DirectivesOpenMP: Heterogenous Execution and Data Movements10.1007/978-3-319-24595-9_11(149-161)Online publication date: 26-Nov-2015
https://doi.org/10.1007/978-3-319-24595-9_11
Kim SLee SJun MLee BRo WChung EGaudiot J(2014)$C\!\!-\!\!Lock$IEEE Transactions on Computers10.1109/TC.2013.8463:8(1962-1974)Online publication date: 1-Aug-2014
https://dl.acm.org/doi/10.1109/TC.2013.84
Yalcin GSobe AHarmanci DVoronin AWamhoff JFelber PUnsal OCristal AFetzer C(2014)Combining Error Detection and Transactional Memory for Energy-Efficient Computing below Safe Operation MarginsProceedings of the 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing10.1109/PDP.2014.61(248-255)Online publication date: 12-Feb-2014
https://dl.acm.org/doi/10.1109/PDP.2014.61
Rughetti DSanzo PPellegrini A(2014)Adaptive Transactional MemoriesProceedings of the 2014 IEEE 3rd Symposium on Network Cloud Computing and Applications (ncca 2014)10.1109/NCCA.2014.25(105-112)Online publication date: 5-Feb-2014
https://dl.acm.org/doi/10.1109/NCCA.2014.25
Atoofian E(2014)Adaptive Snoop Granularity and Transactional Snoop Filtering in Hardware Transactional MemoryCanadian Journal of Electrical and Computer Engineering10.1109/CJECE.2014.231221737:2(76-85)Online publication date: Sep-2015
https://doi.org/10.1109/CJECE.2014.2312217
Akkan HLang MIonkov L(2013)HPC runtime support for fast and power efficient locking and synchronization2013 IEEE International Conference on Cluster Computing (CLUSTER)10.1109/CLUSTER.2013.6702659(1-7)Online publication date: Sep-2013
https://doi.org/10.1109/CLUSTER.2013.6702659
Baldassin Ade Carvalho JGarcia LAzevedo R(2012)Energy-Performance Tradeoffs in Software Transactional MemoryProceedings of the 2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing10.1109/SBAC-PAD.2012.19(147-154)Online publication date: 24-Oct-2012
https://dl.acm.org/doi/10.1109/SBAC-PAD.2012.19
Hunt NSandhu PCeze L(2011)Characterizing the Performance and Energy Efficiency of Lock-Free Data StructuresProceedings of the 2011 15th Workshop on Interaction between Compilers and Computer Architectures10.1109/INTERACT.2011.13(63-70)Online publication date: 12-Feb-2011
https://dl.acm.org/doi/10.1109/INTERACT.2011.13
Fetzer CFelber P(2011)Transactional memory for dependable embedded systemsProceedings of the 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops10.1109/DSNW.2011.5958817(223-227)Online publication date: 27-Jun-2011
https://dl.acm.org/doi/10.1109/DSNW.2011.5958817
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