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Replacing global wires with an on-chip network: a power analysis

Published: 08 August 2005 Publication History

Abstract

This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and voltage scaling, to significantly reduce the energy to send a bit across chip. We develop an analytic model of large chip designs with an on-chip two-dimensional mesh network and estimate the power savings possible in a 70 nm process for two different design points: a circuit-switched ASIC or FPGA design, and a dynamic packet-switched tiled architecture. For circuit-switched networks, achievable power savings are 35--50% for a mesh with 1 mm links. The packet switched designs use multiplexing and signal encoding to reduce the number of link wires required, but the router overhead limits peak wire power savings to around 20% with optimal tile sizes of around 2 mm

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        cover image ACM Conferences
        ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design
        August 2005
        400 pages
        ISBN:1595931376
        DOI:10.1145/1077603
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Published: 08 August 2005

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        Author Tags

        1. on-chip network power model
        2. pipelining
        3. router
        4. tile size
        5. tiled architecture
        6. wire power model

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        • (2017)Temporal codes in on-chip interconnects2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED.2017.8009158(1-6)Online publication date: Jul-2017
        • (2013)New heuristic algorithms for low-energy mapping and routing in 3D NoCInternational Journal of Computer Applications in Technology10.1504/IJCAT.2013.05429747:1(1-13)Online publication date: 1-Jun-2013
        • (2013)Silicon-aware distributed switch architecture for on-chip networksJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2013.03.00859:7(505-515)Online publication date: 1-Aug-2013
        • (2012)Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOIProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228431(398-405)Online publication date: 3-Jun-2012
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        • (2010)An efficient VFI-based NoC architecture using Johnson-encoded Reconfigurable FIFOsNORCHIP 201010.1109/NORCHIP.2010.5669474(1-5)Online publication date: Nov-2010
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