Article

Virtual channels in networks on chip: implementation and evaluation on hermes NoC

Authors:

Leonel Tedesco,

Fernando MoraesAuthors Info & Claims

SBCCI '05: Proceedings of the 18th annual symposium on Integrated circuits and system design

Pages 178 - 183

https://doi.org/10.1145/1081081.1081128

Published: 04 September 2005 Publication History

Abstract

Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congestion in NoCs reduces the overall system performance. This effect is particularly strong in networks where a single buffer is associated with each input channel, which simplifies router design, but prevents packets from sharing a physical channel at any given instant of time. The goal of this work is to describe the implementation of a mechanism to reduce performance penalization due to packet concurrence for network resources in NoCs. One way to reduce congestion is to multiplex a physical channel using virtual channels (VCs). VCs reduce latency and increase network throughput. The insertion of VCs also enables to implement policies for allocating the physical channel bandwidth, which enables to support quality of service (QoS) in applications. This paper has two main contributions. The first is the detailed implementation of a NoC router with a parameterizable number of VCs. The second is the evaluation of latency and throughput in reasonably sized instances of the Hermes NoC (8x8 mesh), with and without VCs. Additionally, the paper compares the features of the proposed router with others employing VCs. Results show that NoCs with VCs accept higher injections rates w.r.t. NoCs without VCs, with a small standard deviation in the latency values, guaranteeing precise packet latency estimation.

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Cited By

Suresh P(2021)Macro and Micro Architectures for Network on ChipDesign Methodologies and Tools for 5G Network Development and Application10.4018/978-1-7998-4610-9.ch003(44-74)Online publication date: 2021
https://doi.org/10.4018/978-1-7998-4610-9.ch003
Moudi MOthman M(2021)A survey on emerging issues in interconnection networksInternational Journal of Internet Technology and Secured Transactions10.1504/ijitst.2021.11351211:2(131-159)Online publication date: 1-Jan-2021
https://dl.acm.org/doi/10.1504/ijitst.2021.113512
Wang HAudsley NHu XChang W(2020)Meshed Bluetree: Time-Predictable Multi-Memory Interconnect for Multi-Core ArchitecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.3012239(1-1)Online publication date: 2020
https://doi.org/10.1109/TCAD.2020.3012239
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Index Terms

Virtual channels in networks on chip: implementation and evaluation on hermes NoC
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
2. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
  2. Integrated circuits
    1. Interconnect
      1. Metallic interconnect
      2. Photonic and optical interconnect

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Published In

cover image ACM Conferences

SBCCI '05: Proceedings of the 18th annual symposium on Integrated circuits and system design

September 2005

271 pages

ISBN:1595931740

DOI:10.1145/1081081

General Chair:
Carlos Galup-Montoro
Federal University of Santa Catarina, Brazil
,
Program Chairs:
Sergio Bampi
Federal University of Rio Grande do Sul, Brazil
,
Alex Orailoglu
University of California, San Diego, CA

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 04 September 2005

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SBCCI05

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SBCCI05: 18th Symposium on Integrated Circuits and System Design

September 4 - 7, 2005

Florianolpolis, Brazil

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

Suresh P(2021)Macro and Micro Architectures for Network on ChipDesign Methodologies and Tools for 5G Network Development and Application10.4018/978-1-7998-4610-9.ch003(44-74)Online publication date: 2021
https://doi.org/10.4018/978-1-7998-4610-9.ch003
Moudi MOthman M(2021)A survey on emerging issues in interconnection networksInternational Journal of Internet Technology and Secured Transactions10.1504/ijitst.2021.11351211:2(131-159)Online publication date: 1-Jan-2021
https://dl.acm.org/doi/10.1504/ijitst.2021.113512
Wang HAudsley NHu XChang W(2020)Meshed Bluetree: Time-Predictable Multi-Memory Interconnect for Multi-Core ArchitecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.3012239(1-1)Online publication date: 2020
https://doi.org/10.1109/TCAD.2020.3012239
Kumar ARao T(2020)Scalable benchmark synthesis for performance evaluation of NoC core mappingMicroprocessors and Microsystems10.1016/j.micpro.2020.10327279(103272)Online publication date: Nov-2020
https://doi.org/10.1016/j.micpro.2020.103272
Parane KPrabhu Prasad BTalawar B(2020)P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGAWireless Personal Communications10.1007/s11277-020-07529-2Online publication date: 19-Jun-2020
https://doi.org/10.1007/s11277-020-07529-2
Mirhosseini ASadrosadati MAghamohammadi FModarressi MSarbazi-Azad H(2019)BARANACM Transactions on Parallel Computing10.1145/32940495:3(1-29)Online publication date: 22-Jan-2019
https://dl.acm.org/doi/10.1145/3294049
de Barros JAyala-Rincon MQuintero C(2019)Application of an Adaptive Genetic Algorithm for Task Mapping Optimisation on a Wormhole-based Real-time Network-on-Chip2019 IX Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC49506.2019.9046081(1-7)Online publication date: Nov-2019
https://doi.org/10.1109/SBESC49506.2019.9046081
Meyer MWang YWatanabe T(2019)Fault-Tolerant Traffic-Aware Routing Algorithm for 3-D Photonic Networks-on-Chip2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)10.1109/MCSoC.2019.00032(172-179)Online publication date: Oct-2019
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Ogleari MYu YQian CMiller EZhao J(2019)String Figure: A Scalable and Elastic Memory Network Architecture2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00016(647-660)Online publication date: Feb-2019
https://doi.org/10.1109/HPCA.2019.00016
Ruaro MMedina HAmory AMoraes F(2018)Software-Defined Networking Architecture for NoC-based Many-Cores2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8351830(1-5)Online publication date: May-2018
https://doi.org/10.1109/ISCAS.2018.8351830
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