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Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture

Published: 04 September 2005 Publication History

Abstract

This paper presents a method of on-chip communication topology synthesis and optimization for a shared multi-bus based architecture. An assumption for the synthesis is that the system has already been partitioned and mapped onto the appropriate components of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. We model the communication behavior of each module as a set of communication lifetime intervals (CLTIs), which are optimized in terms of number of overlaps among them, size of bus width and the minimum number of buses, using ILP (integer linear programming) formulation. We synthesize the communication topology and further optimize the architecture based on the intermodule communication statistics, which are obtained from the system level profiling of an application. The result of applying this approach to the Talking Assistant used in ubiquitous computing application demonstrates the utility of our techniques to synthesize the communication architecture for a complex system.

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Cited By

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  • (2008)A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)10.1109/DELTA.2008.127(405-409)Online publication date: Jan-2008
  • (2007)On-chip bus architecture optimization for multi-core SoC systemsProceedings of the 5th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems10.5555/1778978.1779013(301-310)Online publication date: 7-May-2007
  • (2006)Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraintProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147078(663-668)Online publication date: 24-Jul-2006

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cover image ACM Conferences
SBCCI '05: Proceedings of the 18th annual symposium on Integrated circuits and system design
September 2005
271 pages
ISBN:1595931740
DOI:10.1145/1081081
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 04 September 2005

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Author Tags

  1. algorithms
  2. on-chip communication architecture synthesis
  3. optimization

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SBCCI05
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SBCCI05: 18th Symposium on Integrated Circuits and System Design
September 4 - 7, 2005
Florianolpolis, Brazil

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

View all
  • (2008)A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)10.1109/DELTA.2008.127(405-409)Online publication date: Jan-2008
  • (2007)On-chip bus architecture optimization for multi-core SoC systemsProceedings of the 5th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems10.5555/1778978.1779013(301-310)Online publication date: 7-May-2007
  • (2006)Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraintProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147078(663-668)Online publication date: 24-Jul-2006

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