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Satisfying real-time constraints with custom instructions

Published: 19 September 2005 Publication History

Abstract

Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application of instruction-set extensions to meet timing constraints in real-time embedded systems. In order to satisfy real-time constraints, the worst-case execution time (WCET) of a task should be reduced as opposed to its average-case execution time. Unfortunately, existing custom instruction selection techniques based on average-case profile information may not reduce a task's WCET. We first develop an Integer Linear Programming (ILP) formulation to choose optimal instruction-set extensions for reducing the WCET. However, ILP solutions for this problem are often too expensive to compute. Therefore, we also propose an efficient and scalable heuristic that obtains quite close to the optimal results. Experiment results indicate that suitable choice of custom instructions can reduce the WCET of our benchmark programs by as much as 42% (23.5% on an average).

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Cited By

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  • (2025)Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-VIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.344727933:1(221-233)Online publication date: Jan-2025
  • (2017)Timing Analysis of Tasks on Runtime Reconfigurable ProcessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.257230425:1(294-307)Online publication date: 1-Jan-2017
  • (2016)Extending the WCET Problem to Optimize for Runtime-Reconfigurable ProcessorsACM Transactions on Architecture and Code Optimization10.1145/301405913:4(1-24)Online publication date: 12-Dec-2016
  • Show More Cited By

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      cover image ACM Conferences
      CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
      September 2005
      356 pages
      ISBN:1595931619
      DOI:10.1145/1084834
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 19 September 2005

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      Author Tags

      1. customizable processors
      2. execution time
      3. instruction-set extensions
      4. real-time systems
      5. worst-case

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      CODES+ISSS '05 Paper Acceptance Rate 50 of 200 submissions, 25%;
      Overall Acceptance Rate 280 of 864 submissions, 32%

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      View all
      • (2025)Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-VIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.344727933:1(221-233)Online publication date: Jan-2025
      • (2017)Timing Analysis of Tasks on Runtime Reconfigurable ProcessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.257230425:1(294-307)Online publication date: 1-Jan-2017
      • (2016)Extending the WCET Problem to Optimize for Runtime-Reconfigurable ProcessorsACM Transactions on Architecture and Code Optimization10.1145/301405913:4(1-24)Online publication date: 12-Dec-2016
      • (2013)EpipeJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2013.06.00359:10(1383-1393)Online publication date: 1-Nov-2013
      • (2011)The Instruction-Set Extension ProblemACM Transactions on Reconfigurable Technology and Systems10.1145/1968502.19685094:2(1-28)Online publication date: 1-May-2011
      • (2011)IO-Aware Custom Instruction Exploration for Customizing Embedded ProcessorsFuture Information Technology10.1007/978-3-642-22333-4_7(57-66)Online publication date: 2011
      • (2010)Energy-aware design space exploration of registerfile for extensible processors2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation10.1109/ICSAMOS.2010.5642055(273-281)Online publication date: Jul-2010
      • (2010)Modern development methods and tools for embedded reconfigurable systemsIntegration, the VLSI Journal10.1016/j.vlsi.2009.06.00243:1(1-33)Online publication date: 1-Jan-2010
      • (2009)Worst-Case Execution Time and Energy AnalysisThe Compiler Design Handbook10.1201/9781420043839.ch1(1-1-1-48)Online publication date: 7-Dec-2009
      • (2009)Evaluating design trade-offs in customizable processorsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1629978(244-249)Online publication date: 26-Jul-2009
      • Show More Cited By

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