F. Li
ABSTRACT
Network power optimization is becoming increasingly important as the sizes of the data manipulated by parallel applications and the complexity of inter-processor data communications are continuously increasing. Several hardware-based schemes have been proposed in the past for reducing network power consumption, either by turning off unused communication links or by lowering voltage/frequency in links with low usage. While the prior research shows that these schemes can be effective in certain cases, they share the common drawback of not being able to predict the link active and idle times very accurately. This paper, instead, proposes a compiler-based scheme that determines the last use of communication links at each loop nest and inserts explicit link turn-off calls in the application source. Specifically, for each loop nest, the compiler inserts a turn-off call per communication link. Each turned-off link is reactivated upon the next access to it. We automated this approach within a parallelizing compiler and applied it to eight array-intensive embedded applications.
- L. Benini and G. D. Micheli. Powering networks on chips: energy-efficient and reliable interconnect design for SoCs. In Proc. the 14th International Symposium on Systems Synthesis, 2001. Google Scholar
Digital Library
- N. Eisley and L.-S. Peh. High-level power analysis of on-chip networks. In Proc. the 7th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, September 2004. Google ScholarDigital Library
- W. Gropp, E. Lusk, and A. Skjellum. Using MPI: Portable Parallel Programming with the Message-Passing Interface. MIT Press, 1994. Google ScholarDigital Library
- P. Gupta, L. Zhong, and N. K. Jha. A high-level interconnect power model for design space exploration. In Proc. the IEEE/ACM International Conference on Computer-Aided Design, 2003. Google ScholarDigital Library
- S. Hiranandani, K. Kennedy, and C.-W. Tseng. Compiling Fortran D for MIMD Distributed-Memory Machines. Communications of the ACM, 35(8):66--80, August 1992. Google ScholarDigital Library
- J. S. Kim, M. B. Taylor, J. Miller, and D. Wentzlaff. Energy characterization of a tiled architecture processor with on-chip networks. In Proc. the International Symposium on Low Power Electronics and Design, Aug 2003. Google ScholarDigital Library
- J. Kim and M. Horowitz. Adaptive supply serial links with sub-1V operation and per-pin clock recovery. In Proc. International Solid-State Circuits Conference, Feb. 2002.Google Scholar
- C. S. Patel. Power constrained design of multiprocessor interconnection networks. In Proc. the International Conference on Computer Design, Washington, DC, USA, 1997. Google ScholarDigital Library
- W. Pugh. Counting solutions to Presburger formulas: how and why. In Proc. the ACM SIGPLAN Conference on Programming Language Design and Implementation, Orlando, Florida, 1994. Google ScholarDigital Library
- V. Raghunathan, M. B. Srivastava, and R. K. Gupta. A survey of techniques for energy efficient on-chip communication. In Proc. the 40th Conference on Design Automation, 2003. Google ScholarDigital Library
- L. Shang, L.-S. Peh, and N. K. Jha. Dynamic voltage scaling with links for power optimization of interconnection networks. In Proc. High Performance Computer Architecture, Feb. 2003. Google ScholarDigital Library
- V. Soteriou and L.-S. Peh. Design space exploration of power-aware on/off interconnection networks. In Proc. the 22nd International Conference on Computer Design, Oct. 2004. Google ScholarDigital Library
Index Terms
- Exploiting last idle periods of links for network power management
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