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Tornado warning: the perils of selective replay in multithreaded processors

Published: 20 June 2005 Publication History

Abstract

As future technologies push towards higher clock rates, traditional scheduling techniques that are based on wake-up and select from an instruction window fail to scale due to their circuit complexities. Speculative instruction schedulers can significantly reduce logic on the critical scheduling path, but can suffer from instruction misscheduling that can result in wasted issue opportunities.Misscheduled instructions can spawn other misscheduled instructions, only to be replayed over again and again until correctly scheduled. These "tornadoes" in the speculative scheduler are characterized by extremely low useful scheduling throughput and a high volume of wasted issue opportunities. The impact of tornadoes becomes even more severe when using Simultaneous Multithreading. Misschedulings from one thread can occupy a significant portion of the processor issue bandwidth, effectively starving other threads.In this paper, we propose Zephyr, an architecture that inhibits the formation of tornadoes. Zephyr makes use of existing load latency prediction techniques as well as coarse-grain FIFO queues to buffer instructions before entering scheduling queues. On average, we observe a 23% improvement in IPC performance, 60% reduction in hazards, 41% reduction in occupancy, and 48% reduction in the number of replays compared with a baseline scheduler.

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Cited By

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  • (2009)A complexity-effective microprocessor design with decoupled dispatch queues and prefetchingParallel Computing10.1016/j.parco.2008.12.00835:5(255-268)Online publication date: 1-May-2009
  • (2009)Accurate Instruction Pre-scheduling in Dynamically Scheduled ProcessorsTransactions on High-Performance Embedded Architectures and Compilers II10.1007/978-3-642-00904-4_7(107-127)Online publication date: 22-Apr-2009
  • (2008)A low-complexity microprocessor design with speculative pre-executionJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2008.05.00354:12(1101-1112)Online publication date: 1-Dec-2008

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cover image ACM Conferences
ICS '05: Proceedings of the 19th annual international conference on Supercomputing
June 2005
414 pages
ISBN:1595931678
DOI:10.1145/1088149
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 20 June 2005

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ICS05: International Conference on Supercomputing 2005
June 20 - 22, 2005
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Cited By

View all
  • (2009)A complexity-effective microprocessor design with decoupled dispatch queues and prefetchingParallel Computing10.1016/j.parco.2008.12.00835:5(255-268)Online publication date: 1-May-2009
  • (2009)Accurate Instruction Pre-scheduling in Dynamically Scheduled ProcessorsTransactions on High-Performance Embedded Architectures and Compilers II10.1007/978-3-642-00904-4_7(107-127)Online publication date: 22-Apr-2009
  • (2008)A low-complexity microprocessor design with speculative pre-executionJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2008.05.00354:12(1101-1112)Online publication date: 1-Dec-2008

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