Liang Yang
ABSTRACT
Task to resource mapping problems are encountered during (i) hardware-software co-design and (ii) performance optimization of Network Processor systems. The goal of the first problem is to find the task to resource mapping that minimizes the design cost subject to all design constraints. The goal of the second problem is to find the mapping that maximizes the performance, subject to all architectural constraints. To meet the design goals in performance, it may be necessary to allow multiple packets to be inside the system at any given instance of time and this may give rise to the resource contention between packets. In this paper, a Randomized Rounding (RR) based solution is presented for the task to resource mapping and scheduling problem. We also proposed two techniques to detect and eliminate the resource contention. We evaluate the efficacy of our RR approach through extensive simulation. The simulation results demonstrate that this approach produces near optimal solutions in almost all instances of the problem in a fraction of time needed to find the optimal solution. The quality of the solution produced by this approach is also better than often used list scheduling algorithm for task to resource mapping problem. Finally, we demonstrate with a case study, the results of a Network Processor design and scheduling problem using our techniques.
- K. Chatha and R. Vemuri. Hardware-software partitioning and pipelined scheduling of transformative applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10:193--208, 2002. Google Scholar
Digital Library
- R. Dick, D. Rhodes, and W. Wolf. Tgff: task graphs for free. International Workshop Hardware/Software Codesign, pages 97--101, Mar 1998. Google ScholarDigital Library
- N. P. Forum. Benchmark implementation agreements. Network Processing Forum, http://www.npforum.org/techinfo/IA.Google Scholar
- Intel. Intel application building blocks design guide. http://www.intel.com/design/network/-products/npfamily/sdk.htm.Google Scholar
- A. Kalavade and P. A. Subrahmanyam. Hardware/software partitioning for multi-function systems. IEEE Transactions on CAD of ICs and Systems, 17(9):516--521, Sep 1998. Google ScholarDigital Library
- R. Niemann and P. Marwedel. Hardware software partitioning using integer programming. Electronic Design & Test Conference, pages 473--479, 1996. Google ScholarDigital Library
- M. Palesi and T. Givargis. Multi-objective design space exploration using genetic algorithms. Tenth International Symposium on Hardware/Software Codesign, pages 67--72, May 2002. Google ScholarDigital Library
- A. Prasad, W. Qui, and R. Mahapatra. Hardware software partitioning of multifunction systems. Design Automation for Embedded Systems, Dec 2002.Google Scholar
- P. Raghavan and C. Thompson. Randomized rounding: A technique for provably good algorithms and algorithmic proof. Combinatorica, 7:365--374, 1987. Google ScholarDigital Library
- R. Ramaswamy, N. Neng, and T. Wolf. Application analysis and resource mapping for heterogeneous network processor architectures. Proc. of Third Workshop on Network Processors and Applications (NP-3) in conjunction with Tenth International Symposium on High Performance Computer Architecture (HPCA-10), pages 103--119, Feb 2004.Google Scholar
- L. Thiele, S. Chakraborty, M. Gries, and S. Kunzli. Design space exploration of network processor architectures. First Workshop on Network Processors at the 8th International Symposium on High-Performance Computer Architecture (HPCA8), pages 30--41, 2002.Google Scholar
- H. Vin, J. Mudigonda, J. Jason, E. Johnson, R. Ju, A. Kunze, and R. Lian. A programming environment for packet-processing systems: Design considerations. In the Workshop on Network Processors & Applications - NP3 in conjunction with The 10th International Symposium on High-Performance Computer Architecture, Feb 2004.Google Scholar
Index Terms
- Resource mapping and scheduling for heterogeneous network processor systems
Recommendations
Resource allocation in network processors for network intrusion prevention systems
Networking applications with high memory access overhead gradually exploit network processors that feature multiple hardware multithreaded processor cores along with a versatile memory hierarchy. Given rich hardware resources, however, the performance ...
Balancing register allocation across threads for a multithreaded network processor
PLDI '04: Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementationModern network processors employ multi-threading to allow concurrency amongst multiple packet processing tasks. We studied the properties of applications running on the network processors and observed that their imbalanced register requirements across ...
Balancing register allocation across threads for a multithreaded network processor
PLDI '04Modern network processors employ multi-threading to allow concurrency amongst multiple packet processing tasks. We studied the properties of applications running on the network processors and observed that their imbalanced register requirements across ...
Comments