Tilman Wolf
Ning Weng
ABSTRACT
Network processors (NPs) promise a flexible, programmable packet processing infrastructure for network systems. To make full use of the capabilities of network processors, it is imperative to provide the ability to dynamically adapt to changing traffic patterns and to provide run-time support in the form of a network processor operating system. The differences to existing operating systems and the main challenges lie in the multiprocessor nature of NPs, their on-chip resources constraints, and the real-time processing requirements. In this paper, we explore the key design tradeoffs that need to be considered when designing a network processor operating system. In particular, we explore the performance impact of (1) application analysis for partitioning, (2) network traffic characterization, (3) workload mapping, and (4) run-time adaptation. We present and discuss qualitative and quantitative results in the context of a particular application analysis and mapping framework, but the observations and conclusions are generally applicable to any run-time environment for network processors.
- Baker, Z., and Prasanna, V. K. A methodology for synthesis of efficient intrusion detection systems on FPGAs. In Proc. of the IEEEConference on Field Programmable Custom Computing Machines(Napa, CA, Apr. 2004). Google Scholar
Digital Library
- Elson, J., and Cerpa, A. Internet content adaptation protocol (ICAP). RFC3507, Network Working Group, Apr. 2003. Google ScholarDigital Library
- EZchip Technologies Ltd. NP-110-Gigabit 7-Layer Network Processor. Yokneam, Israel, 2002. http://www.ezchip.com/html/pr_np-1.html.Google Scholar
- Gavrilovska, A., Schwan, K., Nordstrom, O., and Seifu, H. Network processors as building blocks in overlay networks. In Proc. of Hot Interconnects(Stanford, CA, Aug. 2003), ACM, pp. 83--88.Google ScholarCross Ref
- Goglin, S. D., Hooper, D., Kumar, A., and Yavatkar, R. Advanced software framework, tools, and languages for the IXP family. Intel Technology Journal 7, 4 (Nov. 2004), 64--76.Google Scholar
- IBM Corporation. IBMPower Network Processors, 2000. http://www.chips.ibm.com/products/wired/communications/network_processors.html.Google Scholar
- Intel Corporation. Intel Second Generation Network Processor, 2002. http://www.intel.com/design/network/products/npfamily/ixp2400.htm.Google Scholar
- Kohler, E., Morris, R., Chen, B., Jannotti, J., and Kaashoek, M. F. The Clickmodular router. ACMTransactions on Computer Systems 18, 3 (Aug. 2000), 263--297. Google ScholarDigital Library
- Kokku, R., Riché, T., Kunze, A., Mudigonda, J., Jason, J., and Vin, H. A case for run-time adaptation in packet processing systems. In Proc. of the 2nd Workshop on Hot Topics in Networks (HOTNETS-II)(Cambridge, MA, Nov. 2003).Google Scholar
- Lucent Technologies Inc. PayloadPlusTM Fast Pattern Processor, Apr. 2000. http://www.agere.com/support/non-nda/docs/FPPProductBrief.pdf.Google Scholar
- Malloy, B. A., Lloyd, E. L., and Souffa, M. L. Scheduling DAG's for asynchronous multiprocessor execution. IEEE Transactions on Parallel and Distributed Systems 5, 5 (May 1994), 498--508. Google ScholarDigital Library
- Memik, G., and Mangione-Smith, W. H. NEPAL: A framework for efficiently structuring applications for network processors. In Proc. of Second Network Processor Workshop (NP-2) in conjunction with Ninth International Symposium on High Performance Computer Architecture (HPCA-9)(Anaheim, CA, Feb. 2003).Google Scholar
- Motwani, R., and Raghavan, P. Randomized Algorithms. Cambridge University Press, New York, NY, 1995. Google ScholarDigital Library
- Plishker, W., Ravindran, K., Shah, N., and Keutzer, K. Automated task allocation for network processors. In Proc. of Network System Design Conference(Oct. 2004), pp. 235--245.Google Scholar
- Ramaswamy, R., Weng, N., and Wolf, T. Application analysis and resource mapping for heterogeneous network processor architectures. In Proc. of Third Workshop on Network Processors and Applications (NP-3) in conjunction with Tenth International Symposium on High Performance Computer Architecture (HPCA-10)(Madrid, Spain, Feb. 2004), pp. 103--119.Google Scholar
- Ramaswamy, R., Weng, N., and Wolf, T. Analysis of network processing workloads. In Proc. of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)(Austin, TX, Mar. 2005), pp. 226--235. Google ScholarDigital Library
- Shah, N., Plishker, W., and Keutzer, K. NP-Click: A programming model for the intel IXP1200. In Proc. of Second Network Processor Workshop (NP-2) in conjunction with Ninth International Symposium on High Performance Computer Architecture (HPCA-9)(Anaheim, CA, Feb. 2003), pp. 100--111.Google Scholar
- Taylor, D. E., Turner, J. S., Lockwood, J. W., and Horta, E. L. Dynamic hardware plugins: Exploiting reconfigurable hardware for high-performance programmable routers. Computer Networks 38, 3 (Feb. 2002), 295--310. Google ScholarDigital Library
- Teja Technologies. TejaNP Datasheet, 2003. http://www.teja.com.Google Scholar
- Weng, N., and Wolf, T. Profiling and mapping of parallel workloads on network processors. In Proc. of The 20th Annual ACM Symposium on Applied Computing (SAC)(Santa Fe, NM, Mar. 2005), pp. 890--896. Google ScholarDigital Library
- Wolf, T., and Franklin, M. A. CommBench - a telecommunications benchmark for network processors. In Proc. of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)(Austin, TX, Apr. 2000), pp. 154--162. Google ScholarDigital Library
Index Terms
- Design considerations for network processor operating systems
Recommendations
An operating system architecture for network processors
ANCS '05: Proceedings of the 2005 ACM symposium on Architecture for networking and communications systemsNetwork devices have become significantly more complex in recent years, with the most sophisticated current devices incorporating one or more general-purpose CPUs as part of their hardware. The need for such processing capability is motivated by the ...
C Compiler Design for an Industrial Network Processor
OM '01: Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systemsOne important problem in code generation for embedded processors is the design of efficient compilers for ASIPs with application specific architectures. This paper outlines the design of a C compiler for an industrial ASIP for telecom applications. The ...
C Compiler Design for an Industrial Network Processor
One important problem in code generation for embedded processors is the design of efficient compilers for ASIPs with application specific architectures. This paper outlines the design of a C compiler for an industrial ASIP for telecom applications. The ...
Comments