article

A chip prototyping substrate: the flexible architecture for simulation and testing (FAST)

Authors:

Stephen E. Richardson,

Charis Charitsis,

Kunle OlukotunAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 33, Issue 4

Pages 34 - 43

https://doi.org/10.1145/1105734.1105740

Published: 01 November 2005 Publication History

Abstract

We describe a hybrid hardware emulation environment: the Flexible Architecture for Simulation and Testing (FAST). FAST integrates field-programmable gate arrays (FPGAs), microprocessors, and memory to enable rapid prototyping of chip multiprocessors, multithreaded architectures, or other novel computer architectures and chip-level memory systems. FAST combines configurable and fixed-function hardware and software to facilitate rapid prototyping by utilizing components optimized for their particular tasks: FPGAs for interconnect and glue logic; processors for rapid program execution; and SRAMs for fast memory. Unlike software simulators, FAST can simulate complex designs at multi-megahertz speeds regardless of the simulation detail. We illustrate FAST's utility by describing mappings of both a small-scale CMP with speculation support and a large-scale CMP connected using a network. We then show performance results from a very simple, decoupled 4-way CMP executing small test programs.

References

[1]

T. Austin, E. Larson, and D. Ernst "SimpleScalar: An Infrastructure for Computer System Modeling," IEEE Computer Magazine, Feb. 2002, Page(s): 59 --67

Digital Library

[2]

L. A. Barroso, S. Iman, et al., "RPM: a rapid prototyping engine for multiprocessor systems," IEEE Computer Magazine, Feb. 1995, Page(s): 26 --34

Digital Library

[3]

D. C. Bossen, J. M. Tendler, and K. Reick, "Power4 system design for high reliability," IEEE MICRO Magazine, March-April 2002, Page(s): 16--24

Digital Library

[4]

D. Culler and J. P. Singh, Parallel Computer Architecure A Hardware/Software Approach, Morgan Kaufmann Publishers, Inc. San Francisco, CA, 1999

Digital Library

[5]

J. D. Davis, J. Laudon, K. Olukotun, "Maximizing CMT Througput with Mediocre Cores," In Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT), Sept. 2005

Digital Library

[6]

M. Dubois, J. Jeong Y. H. Song, A. Moga, "Rapid hardware prototyping on RPM-2," IEEE Design & Test of Computers, July-Sept. 1998, Page(s): 112--118

Digital Library

[7]

J. Emer, et. al., "Asim: A Performance Model Framework," IEEE Computer Magazine, Feb. 2002, pp: 68--76

Digital Library

[8]

L. Hammond, B. Hubbert, et al., "The Stanford Hydra CMP," IEEE MICRO Magazine, March-April 2000.

Digital Library

[9]

J. R. Hauser and J. Wawrzynek, "Garp: A MIPS Processor with a Reconfigurable Coprocessor," IEEE Workshop on FPGAs for Custom Computing Machines, pp. 24--33, 1997

Digital Library

[10]

C. J. Hughes, et al., "Rsim Simulating Shared-Memory Multiprocessors with ILP Processors," IEEE Computer Magazine, Feb. 2002, pp. 40--49

Digital Library

[11]

J. Huh, et al., "Exploring the Design Space of Future CMPs," PACT, pp. 199--210, Sept. 2001.

Digital Library

[12]

R. Kalla, B. Sinharoy, J. Tendler, "Simultaneouos Multi-threading Implementation in POWER5," Hot Chips 15, Aug 2003

[13]

S. Kapil, "Gemini: A Power-efficient Chip Multi-Threaded (CMT) UltraSPARC® Processor," Hot Chips 15, Aug 2003

[14]

D. Koufaty, D. Marr, "Hyperthreading technology in the netburst microarchitecture," Micro, IEEE, Volume: 23 Issue: 2, March-April 2003, Page(s): 56--65

Digital Library

[15]

V. Krishnan and J. Torrellas, "A Chip Multiprocessor Architecture with Speculative Multithreading," IEEE Transactions on Computers, Special Issue on Multithreaded Architecture, September 1999

Digital Library

[16]

R. Kumar, D. Tullsen, et al., "Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance," The 31st International Symposium on Computer Architecture (ISCA-31), June 2004.

Digital Library

[17]

P. Magnusson, M. Christensson, J. Eskilson, et al., "Simics: A Full System Simulation Platform," IEEE Computer Magazine, February 2002, pages 50--58

Digital Library

[18]

K. Mai, T. Paaske, N. Jayasena, R. Ho, W. Dally, and M. Horowitz, "Smart Memories: A Modular Reconfigurable Architecture," ISCA-27, June 2000.

Digital Library

[19]

D. Matzke, "Will Physical Scalibility Sabotage Performance Gain?," IEEE Computer Magazine, September 1997, page(s) 84--88

Digital Library

[20]

S. Richardson, "MPOC: A Chip Multiprocessor for Embedded Systems," HPL Technical Report, 2002, http://www.hpl.hp.com/techreports/2002/HPL-2002-186.pdf

[21]

M. Rosenblum, E. Bugnion, et al., "Using the SimOS Machine Simulator to Study Complex Computer Systems," ACM Transactions on Modeling and Computer Simulations, vol. 7, no. 1, pages 78--103, Jan. 1997

Digital Library

[22]

K. Sankaralingam, R. Nagarajan, et al., "Exploiting ILP, TLP, and DLP Using Polymorphism in the TRIPS Architecture," ISCA-30, pp. 422--433, June 2003

Digital Library

[23]

G. Sohi, S. Breach, and T. Vijaykumar, "Multiscalar processors," ISCA-22, pp. 414--425, June 1995.

Digital Library

[24]

J. Steffan and T. Mowry, "The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization," Proceedings of the Fourth International Symposium on High-Performance Computer Architecture (HPCA-4), February 2--4, 1998.

Digital Library

[25]

E. Waingold, et. al., "Baring It All to Software: Raw Machines." IEEE Compter, 30(8), pages 80--93, September 1997, MIT/LCS Technical Report TR-709, March 1997.

Digital Library

[26]

D. W. Wall, "Limits of Instruction-Level Parallelism," WRL Research Report 93/6, Digital Western Research Laboratory, Palo Alto, CA, 1993

[27]

R3000/R3001 Designer's Guide, Integrated Device Technology, Inc., 1990

[28]

Altera Development Kits, http://www.altera.com/products/devkits/kit-dev_platforms.jsp

[29]

128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with Versatile I/O Control Data Sheet, http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24961.pdf

[30]

Artesyn Technologies' Processor Blades and Processor subsystems, http://www.artesyncp.com/products/index.html

[31]

PMON5, http://www.carmel.com/pmon/index.html

[32]

GNU GDB, http://www.gnu.org/directory/GNU/gdb.html,

[33]

1Mb X 36 S/DCD Sync Burst SRAMs, http://www.gsitechnology.com/8324183672.pdf

[34]

High-Speed 3.3V 64K x 36 Asynchronous Dual-Port SRAM, http://www.idt.com/products/pages/Multi-Ports-70V658.html

[35]

Mentor Emulation Products, http://www.mentor.com/emulation

[36]

RCM3200 RabbitCore User's Manual, http://www.rabbitsemiconductor.com/products/rcm3200/docs.shtml

[37]

Fujitsu, Motorola, STMicroelectronics, Synopsys, CoWare and Cadence, System-C Version 2.0 User Guide, 2002. Available at http://www.systemc.org

[38]

Xtensa Product Brief, http://www.tensilica.com/Xtensa_PB_1003.pdf

[39]

FPGA Development Boards, http://www.xilinx.com/

[40]

Xilinx Datasheets, http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp

Cited By

Mori HKise K(2014)Design and Performance Evaluation of a Manycore Processor for Large FPGAProceedings of the 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs10.1109/MCSoC.2014.37(207-214)Online publication date: 23-Sep-2014
https://dl.acm.org/doi/10.1109/MCSoC.2014.37
Takamaeda-Yamazaki SSasakawa RSakaguchi YKise K(2011)An FPGA-based scalable simulation accelerator for tile architecturesACM SIGARCH Computer Architecture News10.1145/2082156.208216639:4(38-43)Online publication date: 19-Dec-2011
https://dl.acm.org/doi/10.1145/2082156.2082166
Chen ZPittman RForin ACheung PWawrzynek J(2010)Combining multicore and reconfigurable instruction set extensionsProceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1723112.1723119(33-36)Online publication date: 21-Feb-2010
https://dl.acm.org/doi/10.1145/1723112.1723119
Show More Cited By

Index Terms

A chip prototyping substrate: the flexible architecture for simulation and testing (FAST)

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 33, Issue 4

Special issue: dasCMP'05

November 2005

130 pages

ISSN:0163-5964

DOI:10.1145/1105734

Issue’s Table of Contents

Copyright © 2005 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 November 2005

Published in SIGARCH Volume 33, Issue 4

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Cited By

Mori HKise K(2014)Design and Performance Evaluation of a Manycore Processor for Large FPGAProceedings of the 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs10.1109/MCSoC.2014.37(207-214)Online publication date: 23-Sep-2014
https://dl.acm.org/doi/10.1109/MCSoC.2014.37
Takamaeda-Yamazaki SSasakawa RSakaguchi YKise K(2011)An FPGA-based scalable simulation accelerator for tile architecturesACM SIGARCH Computer Architecture News10.1145/2082156.208216639:4(38-43)Online publication date: 19-Dec-2011
https://dl.acm.org/doi/10.1145/2082156.2082166
Chen ZPittman RForin ACheung PWawrzynek J(2010)Combining multicore and reconfigurable instruction set extensionsProceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1723112.1723119(33-36)Online publication date: 21-Feb-2010
https://dl.acm.org/doi/10.1145/1723112.1723119
Tatas KKyriacou CEvripidou PTrancoso PWong S(2008) Rapid Prototyping of the Data-Driven Chip-Multiprocessor (D 2 -CMP) using FPGAs Parallel Processing Letters10.1142/S012962640800339918:02(291-306)Online publication date: Jun-2008
https://doi.org/10.1142/S0129626408003399
Wee SCasper JNjoroge NTesylar YGe DKozyrakis COlukotun KDeHon AHutton M(2007)A practical FPGA-based framework for novel CMP researchProceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays10.1145/1216919.1216936(116-125)Online publication date: 18-Feb-2007
https://dl.acm.org/doi/10.1145/1216919.1216936

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