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Design, implementation, and verification of active cache emulator (ACE)

Published: 22 February 2006 Publication History

Abstract

This paper presents the design, implementation, and verification of the Active Cache Emulator (ACE), a novel FPGA-based emulator that models an L3 cache actively and in real-time. ACE leverages interactions with its host system to model the target system (i.e. hypothetical system under study). Unlike most existing FPGA-based cache emulators that collect only memory traces from their host system, ACE provides feedback to its host by modeling the impact of the emulated cache on the system. Specifically, delays are injected to time dilate the host system which then experiences hit/miss latencies of the emulated cache. Such active emulation expands the context of performance measurements by capturing processor performance metrics (e.g. cycle per instruction) in addition to measuring the typical cache-specific performance metrics (e.g. miss ratio).ACE is designed to interface with a front-side bus (FSB) of a typical Pentium®-based PC system. To actively emulate cache latencies, ACE utilizes the snoop stall mechanism of the FSB to inject delays to the system. At present, ACE is implemented using a Xilinx XC2V6000 FPGA running at 66MHz, the same speed as its host's FSB. Verification of ACE includes using the Cache Calibrator and RightMark Memory Analyzer software to confirm proper detection of the emulated cache by the host system, and comparing ACE results with SimpleScalar software simulations.

References

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Cited By

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  • (2014)HMTTACM Transactions on Architecture and Code Optimization10.1145/257966811:1(1-25)Online publication date: 1-Feb-2014
  • (2014)DRAC: a dynamically reconfigurable active L1 cache model for hybrid prototyping of multicore embedded systems2014 25nd IEEE International Symposium on Rapid System Prototyping10.1109/RSP.2014.6966897(86-92)Online publication date: Oct-2014
  • (2009)Hardware/Software Co-Simulation for Last Level Cache ExplorationProceedings of the 2009 IEEE International Conference on Networking, Architecture, and Storage10.1109/NAS.2009.66(371-378)Online publication date: 9-Jul-2009
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    cover image ACM Conferences
    FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
    February 2006
    248 pages
    ISBN:1595932925
    DOI:10.1145/1117201
    • General Chair:
    • Steve Wilton,
    • Program Chair:
    • André DeHon
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    Published: 22 February 2006

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    Author Tags

    1. FPGA-based emulator
    2. cache modeling
    3. real-time emulation

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    Cited By

    View all
    • (2014)HMTTACM Transactions on Architecture and Code Optimization10.1145/257966811:1(1-25)Online publication date: 1-Feb-2014
    • (2014)DRAC: a dynamically reconfigurable active L1 cache model for hybrid prototyping of multicore embedded systems2014 25nd IEEE International Symposium on Rapid System Prototyping10.1109/RSP.2014.6966897(86-92)Online publication date: Oct-2014
    • (2009)Hardware/Software Co-Simulation for Last Level Cache ExplorationProceedings of the 2009 IEEE International Conference on Networking, Architecture, and Storage10.1109/NAS.2009.66(371-378)Online publication date: 9-Jul-2009
    • (2008)An open-source HyperTransport coreACM Transactions on Reconfigurable Technology and Systems (TRETS)10.1145/1391732.13917341:3(1-21)Online publication date: 19-Sep-2008
    • (2008)HMTTACM SIGMETRICS Performance Evaluation Review10.1145/1384529.137548436:1(229-240)Online publication date: 2-Jun-2008
    • (2008)HMTTProceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems10.1145/1375457.1375484(229-240)Online publication date: 2-Jun-2008
    • (2007)A practical FPGA-based framework for novel CMP researchProceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays10.1145/1216919.1216936(116-125)Online publication date: 18-Feb-2007
    • (2007)A versatile, low latency HyperTransport coreProceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays10.1145/1216919.1216926(45-52)Online publication date: 18-Feb-2007

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