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The routability of multiprocessor network topologies in FPGAs

Published: 04 March 2006 Publication History

Abstract

A fundamental difference between ASICs and FPGAs is that wires in ASICs are designed such that they match the requirements of a particular design. Wire parameters such as length, width, layout and the number of wires can be varied to implement a desired circuit. Conversely, in an FPGA, area is fixed and routing resources exist whether or not they are used, so the goal becomes implementing a circuit within the limits of available resources. The architecture for existing routing structures in FPGAs has evolved over time to suit the requirements of large, localized digital circuits. However, FPGAs now have the capacity to implement networks of such circuits, and system-level interconnection becomes a key element of the design process.Following a standard design flow and using commercial tools, we investigate how this fundamental difference in resource usage affects the mapping of various network topologies to a modern FPGA routing structure. By exploring the routability of different multiprocessor network topologies with 8, 16 and 32 nodes on a single FPGA, we show that the difference between resource utilization of a ring, star, hypercube and mesh topologies is not significant up to 32 nodes. We also show that a fully-connected network can be implemented with at least 16 nodes, but with 32 nodes it exceeds the routing resources available on the FPGA. We also derive a cost metric that helps to estimate the impact of the topology selection based on the number of nodes.

References

[1]
ARM Corporation. "AMBA specification". {online} 1999. www.arm.com (Accessed: 2005).
[2]
IBM Corporation. "The Coreconnect Bus Architecture", {online} 1999. www.chips.ibm.com (Accessed: 2005).
[3]
OpenCores.org. "The WISHBONE System Architecture". {online} 2002. opencores.org/projects.cgi/web/wishbone (Accessed: 2005).
[4]
Sonics Inc. (online). www.sonicsinc.com/sonics/products/siliconbackplaneIII/ (Accessed: 2005).
[5]
G. de Micheli and L. Benini. Networks on chip: A new paradigm for systems on chip design. In DATE '02: Proceedings of the conference on Design, automation and test in Europe, page 418, Washington, DC, USA, 2002. IEEE Computer Society.
[6]
S. Kumar, A. Jantsch, J. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani. A network on chip architecture and design methodology. In VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on, pages 105--112, Pittsburgh, USA, 2002. IEEE Computer Society.
[7]
Adrijean Adriahantenaina, Herve Charlery, Alain Greiner, Laurent Mortiez, and Cesar Albenes Zeferino. Spin: A scalable, packet switched, on-chip micro-network. In DATE '03: Proceedings of the conference on Design, Automation and Test in Europe, page 20070, Washington, DC, USA, 2003. IEEE Computer Society.
[8]
Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, and Resve Saleh. Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. Comput., 54(8):1025--1040, 2005.
[9]
William J. Dally and Brian Towles. Route packets, not wires: on-chip interconnection networks. In DAC '01: Proceedings of the 38th conference on Design automation, pages 684--689, New York, NY, USA, 2001. ACM Press.
[10]
G. Brebner and D. Levi. Networking on Chip with Platform FPGAs. In Field-Programmable Technology (FPT), Proceedings. 2003 IEEE International Conference on, pages 13--20, July 2003.
[11]
Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, and Serge Goossens. A modular simulation framework for architectural exploration of on-chip interconnection networks. In CODES+ISSS '03: Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pages 7--12, New York, NY, USA, 2003. ACM Press.
[12]
Davide Bertozzi and Antoine Jalabert. NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. IEEE Trans. Parallel Distrib. Syst., 16(2):113--129, 2005.
[13]
Charles L. Seitz. Let's route packets instead of wires. In AUSCRYPT '90: Proceedings of the sixth MIT conference on Advanced research in VLSI, pages 133--138, Cambridge, MA, USA, 1990. MIT Press.
[14]
T.A. Bartic, J.Y. Mignolet, T. Marescaux, D. Verkest, S. Vernalde, and R. Lauwereins. Topology adaptive network-on-chip design and implementation. In Computer and Digital Tecniques, IEEE Proceedings, pages 467--472. IEE Proceedings, July 2005.
[15]
J. Duato and L. Yalamanchili Ni. Interconnection Networks, an Engineering Approach. Computer Society Press, Los Alamitos, California, 1998.
[16]
Xilinx, Inc. http://www.xilinx.com.
[17]
ModelSim Home Page, {online} September 2005. http://www.model.com/.

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  • (2018)Analysis of Approaches for Synthesis of Networks-on-chip by Using Circulant TopologiesJournal of Physics: Conference Series10.1088/1742-6596/1050/1/0120711050(012071)Online publication date: 26-Jul-2018
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cover image ACM Conferences
SLIP '06: Proceedings of the 2006 international workshop on System-level interconnect prediction
March 2006
130 pages
ISBN:1595932550
DOI:10.1145/1117278
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 04 March 2006

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Author Tags

  1. FPGA
  2. interconnect
  3. multiprocessor
  4. network-on-chip
  5. topology

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Cited By

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  • (2020)An Improved Heterogeneous Dynamic List Schedule AlgorithmAlgorithms and Architectures for Parallel Processing10.1007/978-3-030-60245-1_11(159-173)Online publication date: 29-Sep-2020
  • (2018)Development of a Universal Adaptive Fast Algorithm for the Synthesis of Circulant Topologies for Networks-on-Chip Implementations2018 IEEE 38th International Conference on Electronics and Nanotechnology (ELNANO)10.1109/ELNANO.2018.8477462(110-115)Online publication date: Apr-2018
  • (2018)Analysis of Approaches for Synthesis of Networks-on-chip by Using Circulant TopologiesJournal of Physics: Conference Series10.1088/1742-6596/1050/1/0120711050(012071)Online publication date: 26-Jul-2018
  • (2017)On-Chip Networks, Second EditionSynthesis Lectures on Computer Architecture10.2200/S00772ED1V01Y201704CAC04012:3(1-210)Online publication date: 17-Jun-2017
  • (2017)Application of exhaustive search, branch and bound, parallel computing and Monte-Carlo methods for the synthesis of quasi-optimal network-on-chip topologies2017 IEEE East-West Design & Test Symposium (EWDTS)10.1109/EWDTS.2017.8110092(1-6)Online publication date: Sep-2017
  • (2014)A Parameterizable NoC Router for FPGAsJournal of Computers10.4304/jcp.9.3.519-5289:3Online publication date: 1-Mar-2014
  • (2014)A configurable, programmable and software-defined network on chip2014 IEEE Workshop on Advanced Research and Technology in Industry Applications (WARTIA)10.1109/WARTIA.2014.6976396(813-816)Online publication date: Sep-2014
  • (2013)A remote memory access infrastructure for global address space programming models in FPGAsProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435301(211-220)Online publication date: 11-Feb-2013
  • (2013)Hardware MPI-2 Functions for Multi-Processing Reconfigurable System on ChipProceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum10.1109/IPDPSW.2013.147(273-280)Online publication date: 20-May-2013
  • (2011)Leveraging reconfigurability in the hardware/software codesign processACM Transactions on Reconfigurable Technology and Systems10.1145/2000832.20008404:3(1-27)Online publication date: 22-Aug-2011
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