Article

Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture

Authors:

Antonis Papanikolaou,

Francky CatthoorAuthors Info & Claims

SLIP '06: Proceedings of the 2006 international workshop on System-level interconnect prediction

Pages 75 - 81

https://doi.org/10.1145/1117278.1117294

Published: 04 March 2006 Publication History

Abstract

The increasing gap between design productivity and chip complexity, and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable Intellectual Property (IP) cores. The physical design implementation of the macro cells (IP blocks or pre-designed blocks) in general needs to find a well balanced solution among chip area, on-chip interconnect energy and critical path delay. We are especially interested in the entire trade-off curve among these three criteria at the floorplanning stage. We show this concept for a real communication scheme based on segmented bus, rather than just an extreme solution. A fast exploration design flow from the memory organization to the final layout is introduced to explore the design space.

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Cited By

Narang GFell AGupta PGrover A(2015)Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems2015 28th IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2015.7406922(105-110)Online publication date: Sep-2015
https://doi.org/10.1109/SOCC.2015.7406922
Siozios KPapanikolaou ASoudris D(2011)CAD tools for designing 3D integrated systems2011 IEEE International Symposium of Circuits and Systems (ISCAS)10.1109/ISCAS.2011.5938044(2229-2232)Online publication date: May-2011
https://doi.org/10.1109/ISCAS.2011.5938044
Pasricha SPark YKurdahi FDutt N(2010)CAPPSIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200930418:2(209-221)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2009304
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Index Terms

Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
1. Hardware
  1. Integrated circuits

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Published In

cover image ACM Conferences

SLIP '06: Proceedings of the 2006 international workshop on System-level interconnect prediction

March 2006

130 pages

ISBN:1595932550

DOI:10.1145/1117278

General Chair:
Mike Hutton
Altera, USA
,
Program Chair:
Joni Dambre
Ghent University, Belgium

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 04 March 2006

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SLIP06: International Workshop on System Level Interconnect Prediction

March 4 - 5, 2006

Munich, Germany

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Overall Acceptance Rate 6 of 8 submissions, 75%

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Cited By

Narang GFell AGupta PGrover A(2015)Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems2015 28th IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2015.7406922(105-110)Online publication date: Sep-2015
https://doi.org/10.1109/SOCC.2015.7406922
Siozios KPapanikolaou ASoudris D(2011)CAD tools for designing 3D integrated systems2011 IEEE International Symposium of Circuits and Systems (ISCAS)10.1109/ISCAS.2011.5938044(2229-2232)Online publication date: May-2011
https://doi.org/10.1109/ISCAS.2011.5938044
Pasricha SPark YKurdahi FDutt N(2010)CAPPSIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200930418:2(209-221)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2009304
Meyer BThomas D(2009)Rethinking the synthesis of buses, data mapping, and memory allocation for MPSoCDesign Automation for Embedded Systems10.1007/s10617-008-9026-y13:1-2(73-88)Online publication date: 1-Jun-2009
https://dl.acm.org/doi/10.1007/s10617-008-9026-y
Pasricha SDutt N(2008)Synthesis of On-Chip Communication ArchitecturesOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00006-2(185-252)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00006-2
Meyer BThomas DHa SChoi KDutt NTeich J(2007)Simultaneous synthesis of buses, data mapping and memory allocation for MPSoCProceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1289816.1289822(3-8)Online publication date: 30-Sep-2007
https://dl.acm.org/doi/10.1145/1289816.1289822
Guo JPapanikolaou AZhang HCatthoor F(2007)Energy/area/delay tradeoffs in the physical design of on-chip segmented bus architectureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.90075815:8(941-944)Online publication date: 1-Aug-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.900758
Pasricha SPark YKurdahi FDutt NBergamaschi RChoi K(2006)System-level power-performance trade-offs in bus matrix communication architecture synthesisProceedings of the 4th international conference on Hardware/software codesign and system synthesis10.1145/1176254.1176327(300-305)Online publication date: 22-Oct-2006
https://dl.acm.org/doi/10.1145/1176254.1176327

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