skip to main content
10.1145/1117278.1117298acmconferencesArticle/Chapter ViewAbstractPublication PagesslipConference Proceedingsconference-collections
Article

Constant impedance scaling paradigm for interconnect synthesis

Published: 04 March 2006 Publication History

Abstract

On-chip global interconnects perceived as performance limiters for continued scaling of integrated circuits in nano-CMOS regimes highlight the importance of their proper design and optimization. A constant impedance scaling paradigm is proposed for systematic synthesis of complete interconnects physical parameters from system level performance metrics such as delay, power and wiring density. The methodology is illustrated for different system level targets and optimal physical parameters are deduced.

References

[1]
Magen, N, et.al "Interconnect-Power Dissipation in a Microprocessor", proc. Workshop on System Level Interconnect Prediction, pp. 7--13, Feb. 2004.]]
[2]
G. A. Sai-Halasz, "Performance trends in high-end processors," Proc. IEEE, vol. 84, pp. 20--36, Jan. 1995.]]
[3]
D. Sylvester and C. Hu, "Analytical modeling and characterization of deep-submicron interconnect," Proc. IEEE, vol. 89, pp. 634--664, May 2001.]]
[4]
R. Venkatesan, J. A. Davis, K. A. Bowman, and J. D. Meindl, "Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)," IEEE Trans. VLSI Syst., vol. 9, pp. 899--912, Dec. 2001.]]
[5]
A. Naeemi, R. Venkatesan, and J. D. Meindl, "Optimal global interconnecting devices for GSI," IEEE Trans. Electron Devices, vol. 50, pp. 980--987, Apr. 2003.]]
[6]
A. Naeemi, J. A. Davis, and J. D. Meindl, "Analysis and optimization of coplanar RLC lines for GSI," IEEE Trans. Electron Devices, pp. 985--994, June 2004.]]
[7]
Li, XC - Mao, JF - Huang, HF - Liu, Y, "Global Interconnect Width and Spacing Optimization for Latency, Bandwidth and Power Dissipation", IEEE Trans. Electron devices, Vol.52, no.10, pp. 2272--2279, Oct. 2005.]]
[8]
M. A. El-Moursy et al, "Optimum wire sizing of RLC interconnect with repeaters", Journal of VLSI integration, Elsevier Science, no. 38, pp. 205--225, 2004.]]
[9]
J. Balachandran et al., "Constant Impedance Scaling Paradigm for scaling LC transmission lines", Proc. International Symposium on Quality Electronic Design, March 2006.]]
[10]
Richard T. Chang, et.al, "Near Speed of light on-chip Electrical Interconnect", Symposium on VLSI Circuits Digest of Technical papers, 2002.]]
[11]
J. Balachandran et al., "Package Level Interconnect Options", Workshop on System Level Interconnect Prediction, pp. 21--27, Apr. 2005.]]
[12]
Beckmann. B.M., et.al, "TLC: transmission line caches", Proceedings. 36th Annual IEEE/ACM International Symposium on Micro architecture, pp.43--54, Dec. 2003.]]
[13]
D. Chung, "A Chip-Package Hybrid DLL Loop and Clock Distribution Network for Low-Jitter Clock Delivery" ISSCC Dig. Tech. Papers, pp. 514--516, Feb. 2005.]]
[14]
D. M. Pozar, "Microwave Engineering", Reading, MA: Addison-Wesley, 1990.]]
[15]
T. Sakurai, "Closed expressions for interconnection delay, coupling,and crosstalk in VLSIs," IEEE Trans. Electron Devices, vol. 40, pp.118--124, Jan. 1993.]]

Cited By

View all
  • (2006)Constant Impedance Scaling Paradigm for Scaling LC transmission linesProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.38(387-392)Online publication date: 27-Mar-2006

Index Terms

  1. Constant impedance scaling paradigm for interconnect synthesis

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Conferences
      SLIP '06: Proceedings of the 2006 international workshop on System-level interconnect prediction
      March 2006
      130 pages
      ISBN:1595932550
      DOI:10.1145/1117278
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Sponsors

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 04 March 2006

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. global interconnects
      2. interconnect optimization
      3. transmission lines

      Qualifiers

      • Article

      Conference

      SLIP06
      Sponsor:

      Acceptance Rates

      Overall Acceptance Rate 6 of 8 submissions, 75%

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)2
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 12 Jan 2025

      Other Metrics

      Citations

      Cited By

      View all
      • (2006)Constant Impedance Scaling Paradigm for Scaling LC transmission linesProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.38(387-392)Online publication date: 27-Mar-2006

      View Options

      Login options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Media

      Figures

      Other

      Tables

      Share

      Share

      Share this Publication link

      Share on social media