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SAT-based sequential depth computation

Published: 21 January 2003 Publication History

Abstract

Determining the depth of sequential circuits is a crucial step towards the completeness of bounded model checking proofs in hardware verification. In this paper, we formulate sequential depth computation as a logical inference problem for Quantified Boolean Formulas. We introduce a novel technique to simplify the complexity of the constructed formulas by applying simple transformations to the circuit netlist. We also study the structure of the resulting simplified QBFs and construct an efficient SAT-based algorithm to check their satisfiability. We report promising experimental results on some of the ISCAS 89 benchmarks.

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Cited By

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  • (2019)Model Checking of Verilog RTL Using IC3 with Syntax-Guided AbstractionNASA Formal Methods10.1007/978-3-030-20652-9_11(166-185)Online publication date: 28-May-2019
  • (2014)Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTLACM Transactions on Design Automation of Electronic Systems10.1145/267654920:1(1-33)Online publication date: 18-Nov-2014
  • (2009)Enhancing SAT-based sequential depth computation by pruning search spaceProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531632(397-400)Online publication date: 10-May-2009
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cover image ACM Conferences
ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference
January 2003
865 pages
ISBN:0780376609
DOI:10.1145/1119772
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 21 January 2003

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Cited By

View all
  • (2019)Model Checking of Verilog RTL Using IC3 with Syntax-Guided AbstractionNASA Formal Methods10.1007/978-3-030-20652-9_11(166-185)Online publication date: 28-May-2019
  • (2014)Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTLACM Transactions on Design Automation of Electronic Systems10.1145/267654920:1(1-33)Online publication date: 18-Nov-2014
  • (2009)Enhancing SAT-based sequential depth computation by pruning search spaceProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531632(397-400)Online publication date: 10-May-2009
  • (2008)Trading-off SAT search and variable quantifications for effective unbounded model checkingProceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design10.5555/1517424.1517450(1-8)Online publication date: 17-Nov-2008
  • (2006)An Optimum Algorithm for Compacting Error Traces for Efficient Design Error DebuggingIEEE Transactions on Computers10.1109/TC.2006.17455:11(1356-1366)Online publication date: 1-Nov-2006
  • (2006)Computing Over-Approximations with Bounded Model CheckingElectronic Notes in Theoretical Computer Science (ENTCS)10.1016/j.entcs.2005.07.021144:1(79-92)Online publication date: 1-Jan-2006
  • (2006)SAT-Based verification methods and applications in hardware verificationProceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems10.1007/11757283_5(108-143)Online publication date: 22-May-2006
  • (2005)An optimum algorithm for compacting error traces for efficient functional debuggingProceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International10.1109/HLDVT.2005.1568834(177-183)Online publication date: 30-Nov-2005
  • (2005)Computational challenges in bounded model checkingInternational Journal on Software Tools for Technology Transfer (STTT)10.1007/s10009-004-0182-57:2(174-183)Online publication date: 1-Apr-2005
  • (2004)Enhanced Diameter Bounding via StructuralProceedings of the conference on Design, automation and test in Europe - Volume 110.5555/968878.969007Online publication date: 16-Feb-2004
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