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An image retrieval system using FPGAs

Published: 21 January 2003 Publication History

Abstract

The main contribution of this paper is to present an image retrieval system using FPGAs. Given a template image T and a database of a number of Images I1, I2,..., our system lists all images that contain a subimage similar to T. More specifically, a hardware generator in our system creates the Verilog HDL source of a hardware that determines whether Ii has a similar subimage to T for any image Ii and a particular template T. The created Verilog HDL source is embed in an FPGA using the design tool provided by the FPGA vendor. Since the hardware embedded in the FPGA is designed for a particular template T, it is an instance-specific hardware that allows us to achieve extreme acceleration. We evaluate the performance of our image matching hardware using a PCI-connected Xilinx FPGA and a timing analyzer. Since the generated hardware attains up to 3000 speed-up factor over the software solution, our approach is promising.

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Cited By

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  • (2012)Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGAIEICE Transactions on Information and Systems10.1587/transinf.E95.D.2369E95.D:10(2369-2376)Online publication date: 2012
  • (2012)A Rewriting Approach to Replace Asynchronous ROMs with Synchronous Ones for the Circuits with CyclesInternational Journal of Networking and Computing10.15803/ijnc.2.2_2692:2(269-290)Online publication date: 2012
  • (2011)Efficient Exhaustive Verification of the Collatz Conjecture using DSP blocks of Xilinx FPGAsInternational Journal of Networking and Computing10.15803/ijnc.1.1_491:1(49-62)Online publication date: 2011
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cover image ACM Conferences
ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference
January 2003
865 pages
ISBN:0780376609
DOI:10.1145/1119772
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 21 January 2003

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Cited By

View all
  • (2012)Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGAIEICE Transactions on Information and Systems10.1587/transinf.E95.D.2369E95.D:10(2369-2376)Online publication date: 2012
  • (2012)A Rewriting Approach to Replace Asynchronous ROMs with Synchronous Ones for the Circuits with CyclesInternational Journal of Networking and Computing10.15803/ijnc.2.2_2692:2(269-290)Online publication date: 2012
  • (2011)Efficient Exhaustive Verification of the Collatz Conjecture using DSP blocks of Xilinx FPGAsInternational Journal of Networking and Computing10.15803/ijnc.1.1_491:1(49-62)Online publication date: 2011
  • (2011)Hardware Implementation of Neural Networks Based on DSP48 Slice of Virtex-4 FPGAEnergy Procedia10.1016/j.egypro.2011.12.76513(9548-9555)Online publication date: Jan-2011
  • (2009)Design and implementation of a fuzzy-modified ant colony hardware structure for image retrievalIEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews10.1109/TSMCC.2009.202051139:5(520-533)Online publication date: 1-Sep-2009
  • (2008)Unsupervised video shot detection using clustering ensemble with a color global scale-invariant feature transform descriptorJournal on Image and Video Processing10.1155/2008/8607432008(1-10)Online publication date: 1-Jan-2008
  • (2008)Image retrievalACM Computing Surveys10.1145/1348246.134824840:2(1-60)Online publication date: 8-May-2008
  • (2008)Combining flash memory and FPGAs to efficiently implement a massively parallel algorithm for content-based image retrievalInternational Journal of Electronics10.1080/0020721080192367995:7(621-635)Online publication date: Jul-2008
  • (2007)Combining flash memory and fpgas to efficiently implement a massively parallel algorithm for content-based image retrievalProceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications10.5555/1764631.1764660(247-258)Online publication date: 27-Mar-2007
  • (2007)Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image RetrievalReconfigurable Computing: Architectures, Tools and Applications10.1007/978-3-540-71431-6_23(247-258)Online publication date: 2007
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