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HyPE: hybrid power estimation for IP-based programmable systems

Published: 21 January 2003 Publication History

Abstract

This paper presents a novel power estimation scheme for programmable systems consisting of predesigned datapath and memory components. The proposed hybrid methodology yields highly accurate estimates within short runtimes by combining high-level simulation with analytical macromodeling of circuit characteristics. To assess its effectiveness in practice, we implemented our hybrid scheme into a power estimation tool, called HYPE, and applied it to explore various architectural alternatives in the design of a 256-state Viterbi decoder and a Rijndael encryptor. For designs with about 1 million transistors, our estimator terminates within seconds. Compared with industrial gate-level power estimators, our approach is up to 1,000 times faster with 5.4% deviation on average.

References

[1]
M. Barocci, L. Benini, A. Bogliolo, B. Ricco, and G. D. Micheli. "Lookup table power macro-models for behavioral library components." In Proc. IEEE Alessandro Volta Workshop on Low Power Design, Mar. 1999.
[2]
G. Bernacchia and M. C. Papaefthymiou. "Analytical macromodeling for high-level power estimation." In Proc. IEEE International Conference on Computer Aided Design, Nov. 1999.
[3]
D. Brooks, V. Tiwari, and M. Martonosi. "Wattch: A framework for architecture-level power analysis and optimizations." In Proc. 27th International Symposium on Computer Architecture, June 2000.
[4]
Z. Chen, K. Roy, and T. L. Chou. "Power sensitivity-a new method to estimate power dissipation considering uncertain specifications of primary inputs." In Proc. of IEEE International Conference on Computer Aided Design, Nov. 1997.
[5]
S. Gupta and F. N. Najm. "Power macromodeling for high level power estimation." In Proc. 34th Design Automation Conference, June 1997.
[6]
S. Gupta and F. N. Najm. "Analytical model for high level power modeling of combinational and sequential circuits." In Proc. IEEE Alessandro Volta Workshop on Low Power Design, Mar. 1999.
[7]
C. Hsieh, L. Chen, and M. Pedram. "Microprocessor power analysis by labeled simulation." In Design, Automation, and Test in Europe, pages 182--189, Mar. 2001.
[8]
P. Landman. "High level power estimation." In Proc. International Symposium on Low Power Electronics and Design, Aug. 1996.
[9]
M. T. Lee, V. Tiwari, S. Malik, and M. Fujita. "Power analysis and minimization techniques for embedded DSP software." IEEE Trans. VLSI Systems, pages 123--135, Mar. 1997.
[10]
X. Liu and M. C. Papaefthymiou. "A static power estimation methodology for IP-based design." In Design, Automation, and Test in Europe, pages 280--287, Mar. 2001.
[11]
X. Liu and M. C. Papaefthymiou. "A Markov chain sequence generator for power macromodeling" In Proc. IEEE International Conference on Computer Aided Design, Nov. 2002.
[12]
E. Macii, M. Pedram, and F. Somenzi. "High-Level power modeling, estimation, and optimization." IEEE Trans. CAD, Nov. 1998.
[13]
F. N. Najm. "Transition density: A stochastic measure of activity in digital circuits." In Proc. 28th Design Automation Conference, June 1991.
[14]
T. Šimunić, L. Benini, and G. D. Micheli. "Cycle-accurate simulation of energy consumption in embedded systems." In Proc. 36th Design Automation Conference, pages 867--872, June 1999.
[15]
Q. Wu, Q. Qiu, M. Pedram, and C. Ding. "Cycle-accurate macro-models for RT-level power analysis." IEEE Trans. VLSI Systems, Dec. 1998.
[16]
W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. "The design and use of simplepower: A cycle-accurate energy estimation tool." In Proc. 37th Design Automation Conference, June 2000.
[17]
R. Zafalon, M. Rossello, E. Macii, and M. Poncino. "Power macromodeling for a high quality RT-level power estimation." In Proc. International Symposium on Quality Electronic Design, pages 59--63, 2000.

Cited By

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  • (2010)PrEstoProceedings of the 2010 International Conference on Field Programmable Logic and Applications10.1109/FPL.2010.69(310-317)Online publication date: 31-Aug-2010
  • (2010)Power‐Aware Multicore SoC and NoC DesignMultiprocessor System-on-Chip10.1007/978-1-4419-6460-1_8(167-193)Online publication date: 9-Nov-2010
  • (2009)High-Level Power Estimation and AnalysisLow-Power CMOS Circuits10.1201/9781420036503.ch18(1-25)Online publication date: 9-Nov-2009

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cover image ACM Conferences
ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference
January 2003
865 pages
ISBN:0780376609
DOI:10.1145/1119772
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 21 January 2003

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Cited By

View all
  • (2010)PrEstoProceedings of the 2010 International Conference on Field Programmable Logic and Applications10.1109/FPL.2010.69(310-317)Online publication date: 31-Aug-2010
  • (2010)Power‐Aware Multicore SoC and NoC DesignMultiprocessor System-on-Chip10.1007/978-1-4419-6460-1_8(167-193)Online publication date: 9-Nov-2010
  • (2009)High-Level Power Estimation and AnalysisLow-Power CMOS Circuits10.1201/9781420036503.ch18(1-25)Online publication date: 9-Nov-2009

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