Chih-Yang Hsu
ABSTRACT
In this paper, we propose an efficient IP-Level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance into the real power consumption of pattern pairs but still has high accuracy. In order to improve the efficiency of the characterization process, the Monte Carlo approach is used during the estimation of the average power to skip the samples that will not increase the accuracy too much. The experimental result shows the table sizes are only up to 107 entries for ISCAS'85 benchmark circuits and the estimation error is only 2.99% on average using the lookup table.
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Digital Library
- Jiing-Yuan Lin, Wen-Zen Shen, and Jing-Yang Jou. "A Structure-Oriented Power Modeling Technique for Macrocells," IEEE Transactions on VLSI Systems, pp. 380--391, Sep. 1999. Google ScholarDigital Library
- Subodh Gupta and Farid N. Najm. "Power Modeling for High-Level Power Estimation," IEEE Transactions on VLSI Systems, pp. 18--29, Feb. 2000. Google ScholarDigital Library
- Chih-Yang Hsu and Wen-Zen Shen. "Vector Compaction for Power Estimation with Grouping and Consecutive Sampling Techniques," Proceeding of International Symposium on Circuits and Systems, vol. II, pp. 472--475, 2002.Google Scholar
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- An efficient IP-level power model for complex digital circuits
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