Anurag Tiwari
ABSTRACT
This paper describes a structured and area efficient approach for in-situ debugging of application for FPGA based reconfigurable systems. A scan chain is inserted into the hardware design running on the FPGA, which helps in debugging and verification by providing watch-point capability. The scan chain technique proposed is easy to use and has very low overhead. The scan-chain based implementation capitalizes on the capability of newer FPGAs to connect several LUTs serially and configure them as shift registers. The hardware debugging procedure proposed using the shift register LUTs does not require any recompilation of the design to change the watch-point conditions and thus, is very fast. In this paper the area overhead resulting from addition of a scan-chain based watch-point logic is discussed and is compared with other proposed debugging techniques. We observed that this technique has an average area overhead of 46% for the ITC benchmark circuits with varying widths of watch-point signals.
- B. L. Hutchings et. al. A CAD suite for high performance FPGA design, proceedings of IEEE symposium on Field-Programmable Custom Computing Machines, April 1999.]] Google Scholar
Digital Library
- B. L. Hutchings et. al. Unifying Simulation and Execution in a Design enivornment for FPGA Systems IEEE trans on VLSI, Feb'00]] Google ScholarDigital Library
- K. A. Tomko and A. Tiwari. Hardware/Software Co-debugging for Reconfigurable Computing IEEE International High Level Design Validation and Test workshop, Oakland CA, Nov. 2000]] Google ScholarDigital Library
- Virtex FPGA series configuration and readback. Application Note XAPP138, Xilinx San Jose CA, October 2000]]Google Scholar
- Lucent Technologies, ORCA Series 4 FPGAs, Dec 2000]]Google Scholar
- T. Wheeler et. al. Using design-level scan to improve FPGA design observability and controllability for functional verification FPL'01]] Google ScholarDigital Library
- Paul Graham et. al. Instrumenting Bitstreams for Debugging FPGA Circuits, proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2001]] Google ScholarDigital Library
- Xilinx, San Jose CA. ChipScope software and ILA Cores User Manual, v. 1.1. June 2000]]Google Scholar
- Altera, San Jose CA. SignalTap Embedded Logic Analyzer Megafunction, April 2001 ver.2.0]]Google Scholar
- Triscend Inc. E5 Configurable System-on-Chip Platform data sheet, July 2001 (ver. 1.06)]]Google Scholar
- SIDSA Inc, SF CA, FIPSOC#8482; Mixed Signal System-on-Chip.]]Google Scholar
- FIPSOC user manual chapter 7, SIDSA Inc.]]Google Scholar
- P. Graham, Logical Hardware Debuggers for FPGA-Based Systems, PhD Thesis, Brigham Young University, Electrical and Computer Engineering Department, Dec. 2001]] Google ScholarDigital Library
- K. A. Tomko, A. Tiwari, Design Techniques to Implement Reconfigurable Hardware Watch-Points for Hardware/Software Co-Debugging, Proceeding of the Conference on Engineering of Reconfigurable Systems and Algorithms, June 2001.]]Google Scholar
- Altera corp, Stratix Programmable Logic Device Family Data Sheet, version 2.0 April 2002]]Google Scholar
- Xilinx Inc, Virtex-II Platform FPGA Handbook, ver. 1.3 Dec' 01]]Google Scholar
- M. Abramovici, M. A. Breuer, A. D. Friedman. Digital Systems testing and testable design pp. 358 IEEE press 1990]]Google Scholar
- Using Xilinx and Synplify for Incremental Designs (ECO), Xilinx application note XAPP164, Xilinx San Jose, CA 1994]]Google Scholar
- Xilinx Inc, Xilinx 4 Software Manuals.]]Google Scholar
- S. A. Guccione, D. Levi, and P. Sundararajan, JBits: A Java-based interface for reconfigurable computing, Proceedings of the 2nd Annual conference on Military and Aerospace Applications of Programmable Devices and Technologies (MAPLD), September 1999.]]Google Scholar
- Scan-chain based watch-points for efficient run-time debugging and verification of FPGA designs
Recommendations
Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures
This paper presents a method for optimization of board-level scan test with the help of reconfigurable scan-chains (RSCs) implemented in a programmable logic of FPGA. Despite that the RSC concept is a well-known solution for scan-based test time ...
Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions
With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines ...
Run-time generation of partial FPGA configurations
This paper presents and evaluates a method of generating partial bitstreams at run-time for dynamic reconfiguration of sections of an FPGA. The method is intended for use in adaptive embedded systems that employ run-time reconfiguration to achieve high ...
Comments