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A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design

Published: 21 January 2003 Publication History

Abstract

As the CMOS technology enters the very deep submicron era, inter-wire coupling capacitance becomes the dominant part of load capacitance. The coupling effects have brought new challenges to routing algorithms on both delay estimation and optimization. In this paper, we propose a timing-driven global routing algorithm with consideration of coupling effects. The two-phase algorithm based on timing-relax method includes a heuristic Steiner tree algorithm and an optimization algorithm. Experimental results are given to demonstrate the efficiency and accuracy of the algorithm.

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  • (2006)Wire density driven global routing for CMP variation and timingProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233599(487-492)Online publication date: 5-Nov-2006
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cover image ACM Conferences
ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference
January 2003
865 pages
ISBN:0780376609
DOI:10.1145/1119772
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 21 January 2003

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Cited By

View all
  • (2018)Models for Determining the Influence of DFSimulation and Optimization of Digital Circuits10.1007/978-3-319-71637-4_3(137-211)Online publication date: 13-Apr-2018
  • (2018)General Issues of Gate-Level Simulation and Optimization of Digital Circuits with Consideration of Destabilizing FactorsSimulation and Optimization of Digital Circuits10.1007/978-3-319-71637-4_1(1-75)Online publication date: 13-Apr-2018
  • (2006)Wire density driven global routing for CMP variation and timingProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233599(487-492)Online publication date: 5-Nov-2006
  • (2006)Optimizing yield in global routingProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233598(480-486)Online publication date: 5-Nov-2006
  • (2006)Spanning graph-based nonrectilinear steiner tree algorithmsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85086224:7(1066-1075)Online publication date: 1-Nov-2006
  • (2006)Wire Density Driven Global Routing for CMP Variation and Timing2006 IEEE/ACM International Conference on Computer Aided Design10.1109/ICCAD.2006.320162(487-492)Online publication date: Nov-2006
  • (2006)Optimizing Yield in Global Routing2006 IEEE/ACM International Conference on Computer Aided Design10.1109/ICCAD.2006.320161(480-486)Online publication date: Nov-2006
  • (2005)Timing driven track routing considering coupling capacitanceProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120929(1156-1159)Online publication date: 18-Jan-2005
  • (2005)Coupling aware timing optimization and antenna avoidance in layer assignmentProceedings of the 2005 international symposium on Physical design10.1145/1055137.1055144(20-27)Online publication date: 3-Apr-2005
  • (2005)Timing driven track routing considering coupling capacitanceProceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.10.1109/ASPDAC.2005.1466546(1156-1159)Online publication date: 2005
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